vtab.vhd

2008年北京市大学生电子设计竞赛程序源代码[测频率

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity Vtab is 
	PORT(
		clk                       : in      std_logic;
		datain                    : in      std_logic_vector(7 downto 0);
		dis_a,dis_b,dis_c,dis_d   : out     std_logic_vector(4 downto 0)
		);
end;


ARCHITECTURE table of Vtab is

component addbcd 
   port( 
          bcd1   : in   std_logic_vector(15 downto 0);
          bcd2   : in   std_logic_vector(15 downto 0);
          bcd    : out   std_logic_vector(15 downto 0)
          );                           
  end component;

signal t1,t2                        :     std_logic_vector(15 downto 0);
signal dis_1,dis_2,dis_3            :     std_logic_vector(15 downto 0);
signal tmph,tmpl                    :     std_logic_vector(3 downto 0);

begin
process(clk)

begin

if clk 'event and clk ='1' then
tmph<=datain(7 downto 4);
tmpl<=datain(3 downto 0);

case tmph is
       when "0000"=>    t1<="0000000000000000";
       when "0001"=>    t1<="0000000000110001";
       when "0010"=>    t1<="0000000001100010";
       when "0011"=>    t1<="0000000010010100";
       when "0100"=>    t1<="0000000100100101";
       when "0101"=>    t1<="0000000101010111";
       when "0110"=>    t1<="0000000110001000";
       when "0111"=>    t1<="0000001001010001";
       when "1000"=>    t1<="0000001010000010";
       when "1001"=>    t1<="0000001100010100";
       when "1010"=>    t1<="0000001101000101";
       when "1011"=>    t1<="0000001101110110";
       when "1100"=>    t1<="0000010000001000";
       when "1101"=>    t1<="0000010000111001";
       when "1110"=>    t1<="0000010001110000";
       when others=>    t1<="0000010001110000";
end case;


case tmpl is
       when "0000"=>    t2<="0000000000000000";
       when "0001"=>    t2<="0000000000000010";
       when "0010"=>    t2<="0000000000000100";
       when "0011"=>    t2<="0000000000000110";
       when "0100"=>    t2<="0000000000001000";
       when "0101"=>    t2<="0000000000010000";
       when "0110"=>    t2<="0000000000010010";
       when "0111"=>    t2<="0000000000010100";
       when "1000"=>    t2<="0000000000010110";
       when "1001"=>    t2<="0000000000011000";
       when "1010"=>    t2<="0000000000100000";
       when "1011"=>    t2<="0000000000100010";
       when "1100"=>    t2<="0000000000100100";
       when "1101"=>    t2<="0000000000100101";
       when "1110"=>    t2<="0000000000100111";
       when others=>    t2<="0000000000101001";
end case;
 
end if;
end process;


      dis_1<=t1;dis_2<=t2;
 ad1: addbcd port map (dis_1,dis_2,dis_3);
   


    dis_a<='0'&dis_3(15 downto 12);   dis_b<='1'&dis_3(11 downto 8);
    dis_c<='0'&dis_3(7 downto 4);     dis_d<='0'&dis_3(3 downto 0);

end;