sina.vhd

2008年北京市大学生电子设计竞赛程序源代码[测频率

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;


entity sinA is
  port(clk                   : in   std_logic;
       key                   : in   std_logic_vector(11 downto 0);
       datain                : in   std_logic_vector(7 downto 0);  
       dataout               : out  std_logic_vector(7 downto 0)
       );
end;

ARCHITECTURE b of sinA is

TYPE KEY_TYPE IS (k0,k1,k2,k3);
signal state_key: KEY_TYPE;

signal counter                                : std_logic_vector(15 downto 0);
signal clk_d                                  : std_logic;
signal delay                                  : std_logic_vector(7 downto 0);
signal key_tmp                                : std_logic_vector(3 downto 0);
signal outbuff,inbuff,da1_2,da1_4,da1_8       : std_logic_vector(7 downto 0);



begin

inbuff<=datain;
dataout<=outbuff;

process(clk)
    begin
      if rising_edge(clk) then
             counter<=counter+1;
             if counter="0000000000000000" then
                     clk_d<=not clk_d;
             end if;
      end if;
end process;

process (clk_d,state_key)
	begin
		if clk_d 'event and clk_d ='1' then
			case state_key is			
				
				when k0 =>
				    state_key <= k1; 
				when k1 =>
                    if key=0 then 
				         state_key<=k1;
                    else state_key<=k2;
                    end if;
                when k2 =>
					case key is
                	
						when "000001000000" => 
						               key_tmp<="0111";       --sin20
						               state_key <= k3;
						when "000010000000" =>
						               key_tmp<="1000";      --sin40
						              
						               state_key <= k3;
						when "000100000000" =>                --sin60
						               key_tmp<="1001";
						            
						               state_key <= k3;
						when "010000000000" =>                 --sin80
						               key_tmp<="1011";
						               state_key <= k3;
						when "100000000000" =>                  --A
						              key_tmp<="1100";
						               state_key <= k3;
						when "001000000000" =>               --reset
						               state_key <= k1;
									  key_tmp<="1111";								
						when others => state_key <= k1;	
					end case;
					
				when k3 =>
				    delay <= delay + 1;
				    if delay="00000000" then 
                         state_key <= k1;
                    else state_key <= k3;
                    end if; 
               
                when others => state_key <=k1;
			end case;
		end if;
end process;

process(clk_d,inbuff)
begin
if clk_d 'event and clk_d ='1' then
  
  da1_2<='0'&inbuff(7 downto 1);
  da1_4<="00"&inbuff(7 downto 2);
  da1_8<="000"&inbuff(7 downto 3);
end if;
end process;


process(clk_d,key_tmp,da1_2,da1_4,da1_8,inbuff)
begin
if clk_d 'event and clk_d ='1' then

   case key_tmp is
                	
     when "0111" =>     outbuff<=da1_4+da1_8;          --sin20
    
     when "1000" =>  outbuff<=da1_2+da1_8;             --sin40
     
     when "1001" =>  outbuff<=da1_2+da1_4+da1_8;       --sin60
           
     when "1011" =>   outbuff<=inbuff;                 --sin80
   
     when "1100" =>   outbuff<=inbuff;                 --A
    
     when others =>    NULL;
 end case;
end if;
end process;

end;