implied.vhd

来自「<数字逻辑与VHDL设计>代码 作者：STEPHEN BROWN」· VHDL 代码 · 共 18 行

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY implied IS
	PORT ( 	A, B 	: IN 	STD_LOGIC ;
			AeqB	: OUT 	STD_LOGIC ) ;
END implied ;

ARCHITECTURE Behavior OF implied IS	
BEGIN
	PROCESS ( A, B )
	BEGIN
		IF A = B THEN
			AeqB <= '1' ;
		END IF ;
	END PROCESS ;
END Behavior ;