flipflop.vhd

来自「<数字逻辑与VHDL设计>代码 作者：STEPHEN BROWN」· VHDL 代码 · 共 17 行

LIBRARY ieee; 
USE ieee.std_logic_1164.all; 

ENTITY flipflop IS 
	 PORT (	D, Clock 	: IN 	STD_LOGIC ; 
			Q 			: OUT 	STD_LOGIC ) ; 
END flipflop ; 

ARCHITECTURE Behavior OF flipflop IS    
BEGIN
	PROCESS
	BEGIN
		WAIT UNTIL Clock'EVENT AND Clock = '1' ;
		Q <= D ; 
	END PROCESS ; 
END Behavior ;