📄 mini-risc core _opencores_org.mht
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<TD align=3Dright><A class=3Dmenu_section=20
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T=20
class=3Dmenu_section>Overview</A> <FONT=20
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<TD><!-- pf_body_start --><B><FONT =
class=3Dpage_title=20
color=3D#c02020 size=3D+2>Mini-Risc core:=20
Overview</FONT></B>=20
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<TD vAlign=3Dtop><B><FONT =
class=3Dblock_title=20
size=3D+1>Details</FONT></B>
<P>Name: minirisc<BR>Created: 25-Sep-2001=20
10:15:03<BR>Updated: 22-May-2007 =
11:54:15<BR>CVS:=20
<A=20
=
href=3D"http://www.opencores.org/cvsweb.shtml/minirisc/">browse</A>
<P><B><FONT class=3Dblock_title =
size=3D+1>Other=20
project properties</FONT></B>
<P>Category :: <A=20
=
href=3D"http://www.opencores.org/browse.cgi/filter/category_microprocesso=
r">Microprocessor</A><BR>Language=20
:: <A=20
=
href=3D"http://www.opencores.org/browse.cgi/filter/language_verilog">Veri=
log</A><BR>Development=20
status :: <A=20
=
href=3D"http://www.opencores.org/browse.cgi/filter/status_stable">Product=
ion/Stable</A><BR></P></TD>
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<TR>
<TD noWrap><B><FONT class=3Dblock_title=20
size=3D+1>Project maintainers</FONT></B> =
<P>
<LI><A=20
=
href=3D"http://www.opencores.org/people.cgi/info/rudi">Rudolf=20
Usselmann</A>
<P><B><FONT class=3Dblock_title=20
size=3D+1>Statistics</FONT></B><BR></P>
<LI><A=20
=
href=3D"http://www.opencores.org/pstats.cgi/view/minirisc">view</A></LI><=
/TD></TR></TBODY></TABLE></TD></TR></TBODY></TABLE>
<P><B><FONT class=3Dblock_title=20
size=3D+1>Description</FONT></B>=20
<P>This is a Mini-RISC CPU/Microcontroller that =
is=20
compatible with the PIC 16C57 from Microchip. =
Additional=20
information about the instruction set and =
capabilities=20
can be found at: www.microchip.com.<BR>
<P><B><FONT class=3Dblock_title size=3D+1>Legal=20
notice</FONT></B>=20
<P><FONT color=3Dred><BR>PIC, Microchip, etc. =
are=20
Trademarks of Microchip Technology Inc. I have =
no idea=20
if implementing this core will or will not =
violate=20
patents, copyrights or cause any other type of =
lawsuits.=20
I provide this core AS IS, without any =
warranties. If=20
you decide to build this core, you are =
responsible for=20
any legal resolutions, such as patents and =
copyrights,=20
and perhaps others .... This source files may be =
used=20
and distributed without restriction provided =
that all=20
copyright statement are not removed from the =
files and=20
that any derivative work contains the original =
copyright=20
notices and the associated disclaimer. <BR>
<UL>THIS SOURCE FILES ARE PROVIDED "AS IS" AND =
WITHOUT=20
ANY <BR>EXPRESS OR IMPLIED WARRANTIES, =
INCLUDING,=20
WITHOUT <BR>LIMITATION, THE IMPLIED WARRANTIES =
OF=20
MERCHANTIBILITY AND <BR>FITNESS FOR A =
PARTICULAR=20
PURPOSE. <BR></UL></FONT><BR>
<P><B><FONT class=3Dblock_title=20
size=3D+1>Motivation</FONT></B>=20
<P>
<UL>
<LI>A PIC compatible Microcontroller that runs =
a lot=20
faster=20
<LI>Synthesisable and technology independent =
design=20
<LI>Separate (External to the core) Program =
Memory=20
<LI>Options to extend the core </LI></UL>
<P><B><FONT class=3Dblock_title=20
size=3D+1>Compatibility</FONT></B>=20
<P>This design should be fully software =
compatible to=20
the Microchip Implementation of the PIC 16C57, =
except=20
for the following extensions:
<P>
<UL>
<LI>Port A is full 8 bits wide=20
<LI>Hardware stack is 4 level deep [original 2 =
levels]=20
(can be easily expanded)=20
<LI>Executions of instructions that modify the =
PC has=20
became a lot more expensive due to the =
pipeline and=20
execution of instructions on every cycle. Any=20
instruction that writes to the PC (PC as =
destination=20
(f), call, goto, retlw) now takes 4 cycles to =
execute=20
(instead of 2 in the original implementation). =
<LI>The 4 'skip' instructions, remain as in =
the=20
original implementation: 1 cycle if not =
skipped, 2=20
cycles if skipped.=20
<LI>Sampling of IO ports might be off=20
<LI>Timer and watchdog might be off a few =
cycles=20
</LI></UL>
<P><B><FONT class=3Dblock_title=20
size=3D+1>Performance</FONT></B>=20
<P>
<UL>
<LI>About 80Mhz, in a Spartan IIe-50, 30% =
utilization=20
<LI>Single cycle instruction execution, except =
as=20
noted above for PC modifications.=20
<LI>I estimate about 22K gates with the xilinx =
primitives, (excluding Register File and =
Program=20
Memory). A Xilinx Vertex XCV100 can hold 4 of =
this=20
cores and program memory, and still have some =
room=20
left. </LI></UL>
<P><B><FONT class=3Dblock_title =
size=3D+1>Implementing the=20
Core</FONT></B>=20
<P>The only file you should edit if you really =
want to=20
implement this core, is the 'primitives.v' file. =
It=20
contains all parts that can be optimized, =
depending on=20
the technology used. It includes memories, and=20
arithmetic modules. I added a =
primitives_xilinx,v file=20
and xilinx_primitives.zip which contain =
primitives for=20
xilinx.<BR>
<P><B><FONT class=3Dblock_title =
size=3D+1>Status</FONT></B>=20
<P>First version of the core is released. =
Included with=20
the release is also a small test bench and =
several test=20
programs written in assembly. MPLAB from =
Microchip, can=20
be used to compile and develop additional code.
<P>The core can be downloaded from OpenCores CVS =
(see=20
Downloads)<BR>
<P><B><FONT class=3Dblock_title =
size=3D+1>Development=20
tools</FONT></B>=20
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