cpld_mpu1.log

工程中使用的一段资源管理vhdl程序,有简单的分频代码等

Starting EDIF2BLIF....
readEDIF ended normally.

Inspect circuit CPLD_MPU1
    Number of input ports   : 1
    Number of output ports  : 16
    Number of bidir ports   : 0
    Number of instances     : 18
    Number of nets          : 18

No design errors found in circuit CPLD_MPU1

WriteBLIF ended normally.