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<A name="Top"></A><H2 align=center> ispLEVER 6.0.00.33.17.06 Fitter Report File </H2>
<H2 align=center>Copyright(C), 1992-2005, Lattice Semiconductor Corporation</H2>
<H2 align=center>All Rights Reserved</H2>
The Basic/Detailed Report Format can be selected in the dialog box
Tools->Fitter Report File Format...
<A name="Project_Summary"></A><FONT COLOR=maroon><U><B><big>Project_Summary</big></B></U></FONT>
<BR>
Project Name : footpresure
Project Path : E:\raflfile\sd\cpld
Project Fitted on : Wed Feb 18 11:14:10 2009
Device : M4128_92
Package : 128
GLB Input Mux Size : 19
Available Blocks : 8
Speed : -7.5
Part Number : LC4128V-75T128I
Source Format : Pure_VHDL
<font color=green size=4><span class=blink><strong><B>Project 'footpresure' Fit Successfully!</B></strong></span></font>
<A name="Compilation_Times"></A><FONT COLOR=maroon><U><B><big>Compilation_Times</big></B></U></FONT>
<BR>
Prefit Time 0 secs
Load Design Time 0.02 secs
Partition Time 0.00 secs
Place Time 0.00 secs
Route Time 0.00 secs
Total Fit Time 00:00:01
<A name="Design_Summary"></A><FONT COLOR=maroon><U><B><big>Design_Summary</big></B></U></FONT>
<BR>
Total Input Pins 0
Total Logic Functions 16
Total Output Pins 16
Total Bidir I/O Pins 0
Total Buried Nodes 0
Total Flip-Flops 0
Total D Flip-Flops 0
Total T Flip-Flops 0
Total Latches 0
Total Product Terms 15
Total Reserved Pins 0
Total Locked Pins 16
Total Locked Nodes 0
Total Unique Output Enables 0
Total Unique Clocks 0
Total Unique Clock Enables 0
Total Unique Resets 0
Total Unique Presets 0
Fmax Logic Levels -
<A name="Device_Resource_Summary"></A><FONT COLOR=maroon><U><B><big>Device_Resource_Summary</big></B></U></FONT>
<BR>
<B> Device
Total Used Not Used Utilization
-----------------------------------------------------------------------
</B>Dedicated Pins
Clock/Input Pins 4 0 4 --> 0
I/O / Enable Pins 2 0 2 --> 0
I/O Pins 90 16 74 --> 17
Logic Functions 128 16 112 --> 12
Input Registers 92 0 92 --> 0
GLB Inputs 288 0 288 --> 0
Logical Product Terms 640 15 625 --> 2
Occupied GLBs 8 5 3 --> 62
Macrocells 128 16 112 --> 12
Control Product Terms:
GLB Clock/Clock Enables 8 0 8 --> 0
GLB Reset/Presets 8 0 8 --> 0
Macrocell Clocks 128 0 128 --> 0
Macrocell Clock Enables 128 0 128 --> 0
Macrocell Enables 128 0 128 --> 0
Macrocell Resets 128 0 128 --> 0
Macrocell Presets 128 0 128 --> 0
Global Routing Pool 248 0 248 --> 0
GRP from IFB .. 0 .. --> ..
(from input signals) .. 0 .. --> ..
(from output signals) .. 0 .. --> ..
(from bidir signals) .. 0 .. --> ..
GRP from MFB .. 0 .. --> ..
----------------------------------------------------------------------
<Note> 1 : The available PT is the product term that has not been used.
<Note> 2 : IFB is I/O feedback.
<Note> 3 : MFB is macrocell feedback.
<A name="GLB_Resource_Summary"></A><FONT COLOR=maroon><U><B><big>GLB_Resource_Summary</big></B></U></FONT>
<BR>
<B> # of PT
--- Fanin --- I/O Input Macrocells Macrocells Logic clusters
Unique Shared Total Pins Regs Used Inaccessible available PTs used
-------------------------------------------------------------------------------------------
Maximum
GLB 36 *(1) 8 -- -- 16 80 16
</B>-------------------------------------------------------------------------------------------
GLB A 0 0 0 2/11 0 2 0 14 2 2
GLB B 0 0 0 1/12 0 1 0 15 1 1
GLB C 0 0 0 3/11 0 3 0 13 3 3
GLB D 0 0 0 0/12 0 0 0 16 0 0
-------------------------------------------------------------------------------------------
GLB E 0 0 0 0/11 0 0 0 16 0 0
GLB F 0 0 0 0/12 0 0 0 16 0 0
GLB G 0 0 0 8/11 0 8 0 8 7 8
GLB H 0 0 0 2/12 0 2 0 14 2 2
-------------------------------------------------------------------------------------------
TOTALS: 0 0 0 16/92 0 16 0 112 15 16
<Note> 1 : For ispMACH 4000 devices, the number of IOs depends on the GLB.
<Note> 2 : Four rightmost columns above reflect last status of the placement process.
<A name="GLB_Control_Summary"></A><FONT COLOR=maroon><U><B><big>GLB_Control_Summary</big></B></U></FONT>
<BR>
<B> Shared Shared | Mcell Mcell Mcell Mcell Mcell
Clk/CE Rst/Pr | Clock CE Enable Reset Preset
------------------------------------------------------------------------------
Maximum
GLB 1 1 16 16 16 16 16
==============================================================================
</B> GLB A 0 0 0 0 0 0 0
GLB B 0 0 0 0 0 0 0
GLB C 0 0 0 0 0 0 0
GLB D 0 0 0 0 0 0 0
------------------------------------------------------------------------------
GLB E 0 0 0 0 0 0 0
GLB F 0 0 0 0 0 0 0
GLB G 0 0 0 0 0 0 0
GLB H 0 0 0 0 0 0 0
------------------------------------------------------------------------------
<Note> 1 : For ispMACH 4000 devices, the number of output enables depends on the GLB.
<A name="Optimizer_and_Fitter_Options"></A><FONT COLOR=maroon><U><B><big>Optimizer_and_Fitter_Options</big></B></U></FONT>
<BR>
Pin Assignment : Yes
Group Assignment : No
Pin Reservation : No
@Ignore_Project_Constraints :
Pin Assignments : No
Keep Block Assignment --
Keep Segment Assignment --
Group Assignments : No
Macrocell Assignment : No
Keep Block Assignment --
Keep Segment Assignment --
@Backannotate_Project_Constraints
Pin Assignments : No
Pin And Block Assignments : No
Pin, Macrocell and Block : No
@Timing_Constraints : No
@Global_Project_Optimization :
Balanced Partitioning : Yes
Spread Placement : Yes
Note :
Pack Design :
Balanced Partitioning = No
Spread Placement = No
Spread Design :
Balanced Partitioning = Yes
Spread Placement = Yes
@Logic_Synthesis :
Logic Reduction : Yes
Node Collapsing : FMAX
Fmax_Logic_Level : 1
D/T Synthesis : Yes
XOR Synthesis : Yes
Max. P-Term for Collapsing : 16
Max. P-Term for Splitting : 80
Max Symbols : 24
@Utilization_options
Max. % of Macrocells used : 100
@Usercode (HEX)
@IO_Types Default = LVCMOS18 (2)
@Output_Slew_Rate Default = FAST (2)
@Power Default = HIGH (2)
@Pull Default = PULLUP_UP (2)
@Fast_Bypass Default = None (2)
@ORP_Bypass Default = None
@Input_Registers Default = None (2)
@Register_Powerup Default = None
Device Options:
<Note> 1 : Reserved unused I/Os can be independently driven to Low or High, and does not
follow the drive level set for the Global Configure Unused I/O Option.
<Note> 2 : For user-specified constraints on individual signals, refer to the Output,
Bidir and Buried Signal Lists.
<A name="Pinout_Listing"></A><FONT COLOR=maroon><U><B><big>Pinout_Listing</big></B></U></FONT>
<BR>
<B> | Pin | Bank |GLB |Assigned| | Signal|
Pin No| Type |Number|Pad |Pin | I/O Type | Type | Signal name
</B>--------------------------------------------------------------------------
1 | GND | - | | | | |
2 | TDI | - | | | | |
3 |VCCIO0 | - | | | | |
4 | I_O | 0 |B0 | | | |
5 | I_O | 0 |B1 | | | |
6 | I_O | 0 |B2 | | | |
7 | I_O | 0 |B4 | | | |
8 | I_O | 0 |B5 | | | |
9 | I_O | 0 |B6 | * |LVTTL | Output|<A href=#14>BOE9</A>
10 |GNDIO0 | - | | | | |
11 | I_O | 0 |B8 | | | |
12 | I_O | 0 |B9 | | | |
13 | I_O | 0 |B10 | | | |
14 | I_O | 0 |B12 | | | |
15 | I_O | 0 |B13 | | | |
16 | I_O | 0 |B14 | | | |
17 |VCCIO0 | - | | | | |
18 | I_O | 0 |C14 | | | |
19 | I_O | 0 |C13 | | | |
20 | I_O | 0 |C12 | * |LVTTL | Output|<A href=#17>BOE12</A>
21 | I_O | 0 |C10 | | | |
22 | I_O | 0 |C9 | | | |
23 | I_O | 0 |C8 | | | |
24 |GNDIO0 | - | | | | |
25 | I_O | 0 |C6 | | | |
26 | I_O | 0 |C5 | | | |
27 | I_O | 0 |C4 | | | |
28 | I_O | 0 |C2 | * |LVTTL | Output|<A href=#15>BOE10</A>
29 | I_O | 0 |C0 | * |LVTTL | Output|<A href=#16>BOE11</A>
30 |VCCIO0 | - | | | | |
31 | TCK | - | | | | |
32 | VCC | - | | | | |
33 | GND | - | | | | |
34 | I_O | 0 |D14 | | | |
35 | I_O | 0 |D13 | | | |
36 | I_O | 0 |D12 | | | |
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