footpresure_dummylct.lc_

工程中使用的一段资源管理vhdl程序,有简单的分频代码等

[DEVICE]
Family = lc4k;
PartType = LC4128V;
Package = 128TQFP;
PartNumber = LC4128V-75T128I;
Speed = -7.5;
Operating_condition = IND;
EN_Segment = Yes;
Pin_MC_1to1 = No;
Default_Device_Io_Types=LVCMOS18,-;
Voltage = 3.3;

[REVISION]
RCS = "$Header $";
Parent = lc4k128v.lci;
Design = ;
DATE = 02/17/2009;
TIME = 15:35:37;
Source_Format = Pure_VHDL;
Type = ;
Pre_Fit_Time = ;

[IGNORE ASSIGNMENTS]
Pin_Assignments = No;
Pin_Keep_Block = No;
Pin_Keep_Segment = No;
Group_Assignments = No;
Macrocell_Assignments = No;
Macrocell_Keep_Block = No;
Macrocell_Keep_Segment = No;
Pin_Reservation = No;
Block_Reservation = No;
Segment_Reservation = No;
Timing_Constraints = No;
IO_Types = No;

[CLEAR ASSIGNMENTS]
Pin_Assignments = No;
Pin_Keep_Block = No;
Pin_Keep_Segment = No;
Group_Assignments = No;
Macrocell_Assignments = No;
Macrocell_Keep_Block = No;
Macrocell_Keep_Segment = No;
Pin_Reservation = No;
Block_Reservation = No;
Segment_Reservation = No;
Timing_Constraints = No;
IO_Types = No;

[BACKANNOTATE ASSIGNMENTS]
Pin_Assignment = No;
Pin_Block = No;
Pin_Macrocell_Block = No;
Routing = No;
Io_Types = No;

[GLOBAL CONSTRAINTS]
Max_Fanin = 24;
Max_PTerm_Split = 80;
Max_PTerm_Collapse = 16;
Max_Pin_Percent = 100;
Max_Macrocell_Percent = 100;
Max_GLB_Input_Percent = 100;
Logic_Reduction = Yes;
XOR_Synthesis = Yes;
Keep_XOR = No;
DT_Synthesis = Yes;
Node_Collapse = Yes;
Nodes_collapsing_mode = FMAX;
Fmax_Logic_Level = 1;
Use_CE = Yes;
Use_Internal_COM_FB = Yes;
Set_Reset_Swap = No;
Clock_Optimize = No;
EN_Set_Reset_Dont_Care = No;
TOE_AS_IO = No;
Set_Reset_Dont_Care = No;
EN_In_Reg_Optimize = No;
In_Reg_Optimize = Yes;
Run_Time = 0;
Routing_Attempts = 2;
Balanced_Partitioning = Yes;
Spread_Placement = Yes;
Usercode = ;
Usercode_Format = HEX;
Vcc = ;
Dual_Function_Macrocell = 1;
Global_PTOE = Yes;
Hard_Fast_Bypass = No;
Fitter_Effort_Level = LOW;
Auto_buffering_for_high_glb_fanin = Off;
Auto_buffering_for_low_bonded_io = Off;
User_max_glb_fanin = 36;
Adjust_input_assignments = Off;

[LOCATION ASSIGNMENTS]
// Block A
BOE13=pin,118,-,A,9;
BOE14=pin,117,-,A,3;
// Block B
BOE9=pin,9,-,B,7;
// Block C
BOE10=pin,28,-,C,2;
BOE11=pin,29,-,C,5;
BOE12=pin,20,-,C,12;
// Block G
BOE1=pin,93,-,G,0;
BOE2=pin,92,-,G,2;
BOE3=pin,91,-,G,5;
BOE4=pin,90,-,G,7;
BOE5=pin,89,-,G,9;
BOE6=pin,86,-,G,12;
BOE7=pin,85,-,G,1;
BOE8=pin,84,-,G,3;
// Block H
BOE15=pin,107,-,H,6;
BOE16=pin,106,-,H,10;
[PTOE ASSIGNMENTS]

[FAST BYPASS]
Default=NONE;
BYPASS=;

[ORP BYPASS]
default=NONE;

[INPUT REGISTERS]
Default=NONE;
;

[IO TYPES]
BOE1=LVTTL,pin,1,-;
BOE2=LVTTL,pin,1,-;
BOE3=LVTTL,pin,1,-;
BOE4=LVTTL,pin,1,-;
BOE5=LVTTL,pin,1,-;
BOE6=LVTTL,pin,1,-;
BOE7=LVTTL,pin,1,-;
BOE8=LVTTL,pin,1,-;
BOE9=LVTTL,pin,0,-;
BOE10=LVTTL,pin,0,-;
BOE11=LVTTL,pin,0,-;
BOE12=LVTTL,pin,0,-;
BOE13=LVTTL,pin,0,-;
BOE14=LVTTL,pin,0,-;
BOE15=LVTTL,pin,1,-;
BOE16=LVTTL,pin,1,-;

[PLL ASSIGNMENTS]

[RESOURCE RESERVATIONS]
layer=OFF;

[SLEWRATE]
FAST=BOE1,BOE2,BOE3,BOE4,BOE5,BOE6,BOE7,BOE8,BOE9,BOE10,BOE11,BOE12,BOE13,BOE14,BOE15,BOE16;
Default=FAST;

[PULLUP]
Default=UP;

[FITTER RESULTS]
I/O_pin_util = 17;
I/O_pin = 16;
Logic_PT_util = 2;
Logic_PT = 15;
Occupied_MC_util = 12;
Occupied_MC = 16;
Occupied_PT_util = 3;
Occupied_PT = 20;
GLB_input_util = 0;
GLB_input = 0;

[TIMING CONSTRAINTS]
layer=OFF;

[FITTER REPORT FORMAT]
Fitter_Options = Yes;
Pinout_Diagram = No;
Pinout_Listing = Yes;
Detailed_Block_Segment_Summary = Yes;
Input_Signal_List = Yes;
Output_Signal_List = Yes;
Bidir_Signal_List = Yes;
Node_Signal_List = Yes;
Signal_Fanout_List = Yes;
Block_Segment_Fanin_List = Yes;
Postfit_Eqn = Yes;
Page_Break = Yes;
Detailed = No;

[POWER]
Default=HIGH;

[SOURCE_CONSTRAINT_OPTION]

[HARDWARE DEVICE OPTIONS]
Zero_Hold_Time = No;
Signature_Word = ;
Pullup = No;
Slew_Rate = FAST;

[TIMING ANALYZER]
Last_source=;
Last_source_type=Fmax;