footpresure.vho

工程中使用的一段资源管理vhdl程序,有简单的分频代码等

-- VHDL netlist-file
library mach;
use mach.components.all;

library ieee;
use ieee.std_logic_1164.all;
entity CPLD_MPU1 is
  port (
    BOE1 : out std_logic;
    BOE2 : out std_logic;
    BOE3 : out std_logic;
    BOE4 : out std_logic;
    BOE5 : out std_logic;
    BOE6 : out std_logic;
    BOE7 : out std_logic;
    BOE8 : out std_logic;
    BOE9 : out std_logic;
    BOE10 : out std_logic;
    BOE11 : out std_logic;
    BOE12 : out std_logic;
    BOE13 : out std_logic;
    BOE14 : out std_logic;
    BOE15 : out std_logic;
    BOE16 : out std_logic
  );
end CPLD_MPU1;

architecture NetList of CPLD_MPU1 is

  signal VCC_net : std_logic;
  signal GND_net : std_logic;

begin
  VCC_I_I_1:   VCC port map ( X=>VCC_net );
  GND_I_I_1:   GND port map ( X=>GND_net );
  OUT_BOE1_I_1:   OBUF port map ( O=>BOE1, 
            I0=>VCC_net );
  OUT_BOE2_I_1:   OBUF port map ( O=>BOE2, 
            I0=>VCC_net );
  OUT_BOE3_I_1:   OBUF port map ( O=>BOE3, 
            I0=>VCC_net );
  OUT_BOE4_I_1:   OBUF port map ( O=>BOE4, 
            I0=>VCC_net );
  OUT_BOE5_I_1:   OBUF port map ( O=>BOE5, 
            I0=>VCC_net );
  OUT_BOE6_I_1:   OBUF port map ( O=>BOE6, 
            I0=>VCC_net );
  OUT_BOE7_I_1:   OBUF port map ( O=>BOE7, 
            I0=>VCC_net );
  OUT_BOE8_I_1:   OBUF port map ( O=>BOE8, 
            I0=>VCC_net );
  OUT_BOE9_I_1:   OBUF port map ( O=>BOE9, 
            I0=>VCC_net );
  OUT_BOE10_I_1:   OBUF port map ( O=>BOE10, 
            I0=>VCC_net );
  OUT_BOE11_I_1:   OBUF port map ( O=>BOE11, 
            I0=>VCC_net );
  OUT_BOE12_I_1:   OBUF port map ( O=>BOE12, 
            I0=>GND_net );
  OUT_BOE13_I_1:   OBUF port map ( O=>BOE13, 
            I0=>VCC_net );
  OUT_BOE14_I_1:   OBUF port map ( O=>BOE14, 
            I0=>VCC_net );
  OUT_BOE15_I_1:   OBUF port map ( O=>BOE15, 
            I0=>VCC_net );
  OUT_BOE16_I_1:   OBUF port map ( O=>BOE16, 
            I0=>VCC_net );

end NetList;