divfreq.vhd

来自「diviseur de frequence en VHDL」· VHDL 代码 · 共 54 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY DivFreq IS		-- divides the 25 Mhz (40 ns) basic frequency
						-- by 12500000 (3 Hz)
							
	PORT(
		ck,reset: IN STD_LOGIC ;
		q	: OUT INTEGER RANGE 0 TO 12500000;
		aflag : OUT STD_LOGIC;  -- aflag = 0 when the counter value is 0
								-- asynchronous flag
		sflag : OUT STD_LOGIC  -- sflag = 0 when the counter value is 0
								-- synchronous flag

				);
END DivFreq;

ARCHITECTURE archi OF DivFreq IS
SIGNAL test:INTEGER RANGE 0 TO 12500000;
SIGNAL aa_flag,ss_flag : STD_LOGIC; 
BEGIN
PROCESS(ck,reset)
BEGIN
IF reset= '0' THEN test<= 0;
ELSIF (ck'EVENT AND ck ='1') THEN 
	IF test = 0 THEN test <= 12500000;
	ELSE test <= test-1;
	END IF;
ELSE test <= test;
END IF;     
END PROCESS;
   
q<= test;  -- the ouputs

PROCESS(test)   --generates the asynchronous flag output 
BEGIN
IF test = 0 THEN aa_flag<='0' ; ELSE aa_flag<='1'; END IF;
END PROCESS;

PROCESS(reset,ck)   --generates the synchronous flag output 
BEGIN
IF reset= '0' THEN ss_flag<= '0';
ELSIF (ck'EVENT AND ck ='1') THEN 
IF aa_flag = '0' THEN ss_flag<='0' ; ELSE ss_flag<='1'; END IF;
ELSE ss_flag <= ss_flag;
END IF;
END PROCESS;

aflag<= aa_flag;
sflag <= ss_flag;

END archi;