atan_lut.vhd

基于改进的查找表的arctan计算模块

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity atan_lut is
	port(
		clk : in std_logic;  -- 时钟
		reset_n : in std_logic; -- 复位
		start : in std_logic; -- 开始信号
		xx : in std_logic_vector(9 downto 0);
		yy : in std_logic_vector(9 downto 0);
		zz : out std_logic_vector(15 downto 0)); ---- 输出 1.1.14
end entity;

architecture rtl of atan_lut is
	-- 除法器
	component div16 IS
	PORT
	(
		clock		: IN STD_LOGIC ;  
		denom		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);  
		numer		: IN STD_LOGIC_VECTOR (17 DOWNTO 0);
		quotient		: OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
		remain		: OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
	);
	END component div16;
	
	component lut_core is
	port(
		clk : in std_logic;
		reset_n : in std_logic;
		start : in std_logic;
		input : in std_logic_vector(17 downto 0);
		result : out std_logic_vector(15 downto 0);
		rslt_ok : out std_logic);
	end component lut_core;
	
	type mstate is (s_idle,s0,s1,s2);
	signal state : mstate;  -- 状态机
	signal flag : std_logic;  
	signal quout : std_logic_vector(17 downto 0); -- 商
	signal remout : std_logic_vector(8 downto 0);
	signal remout0 : std_logic_vector(8 downto 0);
	signal start_core : std_logic;  -- 给核的起始信号
	signal rslt_raw : std_logic_vector(15 downto 0); -- 核的输出
	signal rslt_ok : std_logic;
	signal ov : std_logic;
	signal core_in : std_logic_vector(17 downto 0);
	signal numer : std_logic_vector(17 downto 0);
	signal cnt : integer range 0 to 7;
begin

-- 端口映射
div: div16
	port map(
		clock => clk,
		denom => xx(8 downto 0),
		numer => numer,
		quotient => quout,
		remain => remout);

lc : lut_core
	port map(
		clk => clk,
		reset_n => reset_n,
		start => start_core,
		input => core_in,
		result => rslt_raw,
		rslt_ok => rslt_ok);
		
	numer <= yy(8 downto 0) & "000000000";
	process(clk,reset_n)
	begin
		if reset_n = '0' then
			zz <= (others => '0');
			state <= s_idle;
			flag <= '0';
			start_core <= '0';
			ov <= '0';
			core_in <= (others => '0');
			remout0 <= (others => '0');
			cnt <= 0;
		else
			if clk'event and clk = '1' then
				start_core <= '0';
				case state is
					when s_idle =>
						if start = '1' then
							flag <= xx(9) xor yy(9); -- 存输入的符号，假定输入为原码
							if xx(8 downto 0) /= "000000000" then
								ov <= '0';
							else
								ov <= '1';
							end if;
							cnt <= 4;
							state <= s0;
						end if;
					when s0 =>
						if cnt > 0 then
							cnt <= cnt - 1;
						else
							core_in <= quout;
							remout0 <= remout;
							state <= s1;
						end if;
					when s1 =>
						if remout0 > ('0' & xx(8 downto 1)) then
							core_in <= core_in + 1;
						end if;
						start_core <= '1';
						state <= s2;
					when s2 =>
						if rslt_ok = '1' then
							if ov = '0' then
								zz <= flag & rslt_raw(15 downto 1); --得出结果
							else
								zz <= flag & "110010010001000";
							end if;
							state <= s_idle;
						end if;
					when others =>
						state <= s_idle;
				end case;
			end if;
		end if;
	end process;
end rtl;