usart.vhd

USART coded in VHDL. It is writted in 5 files. I am uploading the files in order.

			--	TOP MODULE :USART:

library ieee;
use ieee.std_logic_1164.all;
use work.components.all;

entity usart is
port(	dmp_pin			: inout	std_logic_vector(7 downto 0);
			reset_pin		: in		std_logic;
			clk_pin			: in		std_logic;
			cd_pin			: in		std_logic;
			rd_pin			: in		std_logic;
			wr_pin			: in		std_logic;
			cs_pin			: in		std_logic;
			dsr_pin			: in		std_logic;
			dtr_pin			: out		std_logic;
			cts_pin			: in		std_logic;
			rts_pin			: out		std_logic;
			txd_pin			: out		std_logic;
			txrdy_pin		: out		std_logic;
			txe_pin			: out		std_logic;
			txclk_pin		: in		std_logic;
			rxrdy_pin		: out		std_logic;
			rxclk_pin		: in		std_logic;
			syndet_pin	: inout	std_logic;	
			rxd_pin			: in		std_logic );
end usart;

architecture usart_arc of usart is
	
signal	drd						: std_logic_vector(7 downto 0);
signal	dwr						: std_logic_vector(7 downto 0);
signal  ciport				: std_logic_vector(7 downto 0);
signal	miport				: std_logic_vector(7 downto 0);
signal	syn1port			: std_logic_vector(7 downto 0);
signal	syn2port			: std_logic_vector(7 downto 0);
signal	holdport			: std_logic_vector(7 downto 0);
signal	writeport			: std_logic_vector(7 downto 0);
signal	statusport		: std_logic_vector(7 downto 0);	   
signal	holdreg_emp		: std_logic;
signal	modemclear		: std_logic;							 
signal	en						: std_logic; 
signal  txe_status		: std_logic;
signal  hold_cts			: std_logic;						
signal  parity_error	: std_logic;
signal  framing_error	: std_logic;
signal  overrun_error	: std_logic;
signal  status_read		: std_logic;
signal  data_read			: std_logic; 
signal  rxrdy_status	: std_logic;
signal  syndet_status	: std_logic;

begin												
													
DBB:data_bus_buffer port map(	dmp		=> 	dmp_pin,
			  											drd		=>	drd,
															dwr		=> 	dwr,
															en		=> 	en );

RWLC:rd_wr_control port map(reset	=> 	reset_pin,
										clk						=>	clk_pin,
										cd						=> 	cd_pin,
										rd						=> 	rd_pin,
										wr						=> 	wr_pin,
										cs						=> 	cs_pin,
										drd						=> 	drd,
										dwr						=> 	dwr,
										ciport				=> 	ciport,
										miport				=> 	miport,
										syn1port			=> 	syn1port,
										syn2port			=> 	syn2port,
										holdport			=> 	holdport,
										writeport 		=> 	writeport,
										statusport		=> 	statusport,
										en						=> 	en,
										holdreg_emp		=> 	holdreg_emp,
										hold_cts			=> 	hold_cts,
										cts						=> 	cts_pin,
										dsr						=> 	dsr_pin,
										txe_status		=> 	txe_status,
										syndet_status	=> 	syndet_status,
										rxrdy_status	=> 	rxrdy_status,
										parity_error	=> 	parity_error,
										framing_error	=> 	framing_error,
										overrun_error	=> 	overrun_error,
										status_read		=> 	status_read,
										data_read			=> 	data_read );
	
MC : modem_control port map(dsr		=> 	dsr_pin,
										dtr						=> 	dtr_pin,
										cts						=> 	cts_pin,
										rts						=> 	rts_pin,
										modemclear		=> 	modemclear,
										ciport				=> 	ciport );
																			  	
TB : tx_buff port map(ciport			=> 	ciport,
										miport				=>	miport,
										syn1port			=>	syn1port,
										syn2port			=>	syn2port,
										holdport			=> 	holdport,
										statusport		=> 	statusport,
										holdreg_emp		=> 	holdreg_emp,
										txclk					=> 	txclk_pin,
										txrdy					=> 	txrdy_pin,
										txe						=> 	txe_pin,
										txe_status		=> 	txe_status,
										txd						=> 	txd_pin,
										modemclear		=> 	modemclear,
										clk						=> 	clk_pin,
										hold_cts			=> 	hold_cts );
	
RB : rec_buf port map(ciport			=> 	ciport,
										miport				=> 	miport,
										syn1port			=> 	syn1port,
										syn2port			=> 	syn2port,
										statusport		=> 	statusport,
										writeport			=> 	writeport,
										rxclk					=> 	rxclk_pin,
										rxrdy					=> 	rxrdy_pin,
										rxd						=> 	rxd_pin,
										syndet 				=> 	syndet_pin,
										parity_error	=> 	parity_error,
										framing_error	=> 	framing_error,
										overrun_error => 	overrun_error,
										syndet_status	=> 	syndet_status,
										status_read		=> 	status_read,
										data_read			=> 	data_read,
										rxrdy_status	=> 	rxrdy_status );
	
end usart_arc;