tx_buff.vhd

USART coded in VHDL. It is writted in 5 files. I am uploading the files in order.

				--			TRANSMIT BLOCK

library ieee;
use ieee.std_logic_1164.all;

entity tx_buff is	
port(	ciport			: in		std_logic_vector(7 downto 0);
			miport			: in		std_logic_vector(7 downto 0);
			syn1port		: in		std_logic_vector(7 downto 0);
			syn2port		: in		std_logic_vector(7 downto 0);
			holdport		: in		std_logic_vector(7 downto 0);
			statusport	: in		std_logic_vector(7 downto 0);  
			holdreg_emp	: out		std_logic;
			txclk				: in		std_logic;
			txrdy				: out		std_logic;
			txe					: out		std_logic;
			txd					: out		std_logic; 
			modemclear	: in		std_logic;
			clk					: in		std_logic;
			hold_cts		: in		std_logic;
			txe_status	: out		std_logic );
end tx_buff;

architecture tb_arc of tx_buff is	   

	type serial is ( start, dbits,parity, stop );
	signal 	shiftreg	: std_logic_vector(7 downto 0);
	signal 	currtxd		: serial		:=stop;
	signal 	nexttxd		: serial		:=stop;
	signal 	i					: integer		:= 0;
	signal 	epar			: std_logic	:='0';
	signal 	len				: integer;
	signal 	shift_emp	: std_logic	:= '1';	   
	signal	hold_emp 	: std_logic	:= '1';	
	signal 	baud			: integer		:=1;
	signal 	count			: integer		:=1; 
	signal 	shift_full: std_logic	:= '0';
	signal 	tstop			: std_logic	:='0';
	signal 	d					: std_logic	:= '0';
begin 
	
	len <= 	5 when miport(3 downto 2) = "00" else
					6 when miport(3 downto 2) = "01" else
					7 when miport(3 downto 2) = "10" else
					8; 										 
			
	baud <= 1  when miport(1 downto 0) = "01" else
					16 when miport(1 downto 0) = "10" else
					64 when miport(1 downto 0) = "11" else
					1;
		 
	holdreg_emp <= hold_emp;	

	process ( clk, ciport(0), modemclear, hold_emp )
	begin
		if modemclear = '1' and ciport(0) = '1' then
			txrdy <= hold_emp;
		else
			txrdy <= '0';
		end if;			 
	end process;   

	process ( clk, modemclear, ciport(0), shift_emp, hold_emp, shiftreg, statusport(0))
	begin
		if (shiftreg = syn1port or shiftreg = syn2port) and statusport(0) = '1' then
			txe <= '1';
			txe_status <= '1';
		elsif shift_emp = '1' and hold_cts = '0' then
			txe <= '1';		  
			txe_status <= '1';
		else	
			txe <= shift_emp and hold_emp;
			txe_status <= shift_emp and hold_emp;
		end if;
	end process;
			
	process(txclk)
	begin
	if txclk = '0' and txclk'event then
		if miport(1 downto 0) = "01" or miport(1 downto 0) = "10" or miport(1 downto 0) = "11" then
			if count = baud then
				count <= 1;
				case currtxd is
					when start => 			  
						i <= 0;
						epar <= '0';
						txd <= '0';
						nexttxd <= dbits;
	
					when dbits =>
						if ciport(3) = '0' then
							txd <= shiftreg(i);
						else
							txd <= '0';
						end if;
						epar <= epar xor shiftreg(i);
						if i <= len-2 then	  
							i <= i+1;
							nexttxd <= dbits;
						elsif miport(4) = '1' then
							i <= 0;
							nexttxd <= parity;
						else	 			  
							i <= 0;
							nexttxd <= stop;
						end if;				 

					when parity =>		
						if ciport(3) = '0' then
							if miport(5) = '1' then
								txd <= epar;
							else
								txd <= not epar;
							end if;	  			   
						else
							txd <= '0';	
						end if;
						i <= 0; 
						epar <= '0';
						nexttxd <= stop; 

					when stop =>			
						i <= 0;
						epar <= '0';
						if ciport(3) = '1' then
							txd <= '0';	
						else
							txd <= '1';
						end if;
						if miport(7) = '1' and tstop = '0' then
							nexttxd <= stop;
							tstop <= '1';
						elsif hold_emp = '1' and shift_emp = '1' and modemclear = '0' then
							nexttxd <= stop;
						elsif shift_emp = '0' then
							nexttxd <= start;
							tstop <= '0';
						else				  
							nexttxd <= stop;
						end if;	
				end case;										
			else
				count <= count+1; 
			end if;
		elsif miport(1 downto 0) = "00" then
			case currtxd is
				when start | dbits =>
					if ciport(3) = '1' then
						txd <= '0';
						nexttxd <= nexttxd;
					else
						txd <= shiftreg(i);
						epar <= epar xor shiftreg(i);
						if i <= len-2 then
							i <= i+1;
							nexttxd <= dbits;	  
						elsif miport(4) = '1' then
							i <= 0;
							nexttxd <= parity;
						elsif shift_emp = '0' then
							i <= 0;		
							nexttxd <= start;
						elsif hold_emp = '1' and shift_emp = '1' and modemclear = '0' then
								nexttxd <= stop;
						end if;
					end if;

				when parity =>		   
					if ciport(3) = '0' then
						if miport(5) = '1' then
							txd <= epar;
						else
							txd <= not epar;
						end if;		
					else
						txd <= '0';
					end if;
					i <= 0;
					epar <= '0';
					if hold_emp = '1' and shift_emp = '1' and modemclear = '0' then
						nexttxd <= stop;
					elsif shift_emp = '0' then	
						nexttxd <= start;
					end if;
						
				when stop =>
					i <= 0;	
					if ciport(3) = '0' then
						txd <= '1';			   
					else 
						txd <= '0'; 
					end if;
					if hold_emp = '1' and shift_emp = '1' and modemclear = '0' then
						nexttxd <= stop;
					elsif shift_emp = '0' then
						nexttxd <= start;
					end if; 				
			end case;
		end if;
	end if;
	end process;

	process ( txclk )
	begin
		if ciport(0) = '1' then
			currtxd <= nexttxd; 
		else
			currtxd <= stop;
		end if;
	end process;   
	
	process ( txclk )
	begin
		if txclk = '1' and txclk'event then	 
			if i=len-1 and currtxd = dbits then
				shift_full <= '0';
			elsif shift_emp = '0' then
				shift_full <= '1';
			end if;
		end if;
	end process;
		
	process( txclk )
	begin		  
		if txclk = '0' and txclk'event then
			if shift_full = '0' and statusport(0) =  '0' then
					if miport(7) = '0' and shiftreg = syn1port then
						shiftreg <= syn2port;
						shift_emp <= '0'; 
						hold_emp <= '0';							
					elsif (hold_cts = '1' or modemclear = '1') and d = '1' then
						shiftreg <= holdport;
						shift_emp <= '0'; 
						hold_emp <= '1';
					else												 
						d <= '1';
						shift_emp <= '1'; 
						hold_emp <= '0';							
					end if;
			elsif shift_full = '0' and statusport(0) = '1' then
					if miport(1 downto 0) = "00" and modemclear = '1'then
						if miport(7) = '0' and shiftreg = syn1port then
							shiftreg <= syn2port;
							shift_emp <= '0'; 
							hold_emp <= '1';							
					 	else
							shiftreg <= syn1port; 
							shift_emp <= '0';
							hold_emp <= '1';
						end if;
					else
						shift_emp <= '1';
						hold_emp <= '1';
					end if;
			elsif shift_full = '1' and statusport(0) = '0' then
					hold_emp <= '0';
					shift_emp <= '0';
			elsif shift_full = '1' and statusport(0) = '1' then
					hold_emp <= '1';
					shift_emp <= '0';
			end if;
		end if;
	end process;

end tb_arc;