rd_wr_control.vhd

USART coded in VHDL. It is writted in 5 files. I am uploading the files in order.

					--		READ/WRITE CONTROL LOGIC

library ieee;
use ieee.std_logic_1164.all;

entity rd_wr_control is
port( reset					: in	std_logic;
			clk						: in	std_logic;
			cd						: in	std_logic;
			rd						: in	std_logic;
			wr						: in	std_logic;
			cs						: in	std_logic;
			drd						: in	std_logic_vector(7 downto 0);
			dwr						: out	std_logic_vector(7 downto 0);
			ciport				: out	std_logic_vector(7 downto 0);
			miport				: out	std_logic_vector(7 downto 0);
			syn1port			: out	std_logic_vector(7 downto 0);
			syn2port			: out	std_logic_vector(7 downto 0);
			holdport			: out	std_logic_vector(7 downto 0);
			writeport 		: in	std_logic_vector(7 downto 0);
			statusport		: out	std_logic_vector(7 downto 0);
			en						: out	std_logic; 
			holdreg_emp 	: in	std_logic;
			cts						: in	std_logic;
			dsr						: in  std_logic;
			hold_cts			: out std_logic;
			txe_status		: in	std_logic;
			syndet_status	: in	std_logic;
			rxrdy_status	: in 	std_logic;
			parity_error	: in 	std_logic;
			framing_error	: in	std_logic;
			overrun_error	: in	std_logic;
			status_read		: out	std_logic;
			data_read			: out	std_logic );
end rd_wr_control;

architecture rwc_arc of rd_wr_control is

	type states is (resets, modes, commands, syn1s, syn2s, status, reads, writes, tristate);
	signal currstate 	: states;
	signal nextstate 	: states;
	signal mireg 			: std_logic_vector(7 downto 0);	
	signal cireg			: std_logic_vector(7 downto 0);
	signal syn1reg		: std_logic_vector(7 downto 0);
	signal syn2reg		: std_logic_vector(7 downto 0);
	signal holdreg 		: std_logic_vector(7 downto 0);
	signal writereg		: std_logic_vector(7 downto 0);
	signal statusreg	: std_logic_vector(7 downto 0);

begin					 

		miport   <= mireg;
		ciport   <= cireg;
		syn1port <= syn1reg;
		syn2port <= syn2reg;
		holdport <= holdreg;
		statusport <= statusreg; 
		writereg <= writeport;	 

	process ( currstate, cd, rd, wr, cs, mireg, cireg )
	begin 			 
		case currstate is
			when resets =>
				nextstate <= modes;

			when modes =>
			   if mireg(1 downto 0) = "00" then
					nextstate <= syn1s;
				else
					nextstate <= commands;
				end if;

			when syn1s =>
				if mireg(7) = '0' then
					nextstate <= syn2s;
				else
					nextstate <= commands;
				end if;

			when syn2s =>
				nextstate <= commands;

			when commands =>
				if cireg(6) = '1' then
					nextstate <= modes;
				elsif cs = '0' and wr = '0' and rd = '1' and cd = '1' then
					nextstate <= commands;
				elsif cs = '0' and wr = '1' and rd = '0' and cd = '0' then
					nextstate <= writes;
				elsif cs = '0' and wr = '0' and rd = '1' and cd = '0' then
					nextstate <= reads;
				elsif cs = '0' and wr = '1' and rd = '0' and cd = '1' then
					nextstate <= status;
				else 
					nextstate <= tristate;
				end if;

			when others =>
				if cireg(6) = '1' then
					nextstate <= modes;
				elsif cs = '0' and wr = '0' and rd = '1' and cd = '1' then
					nextstate <= commands;
				elsif cs = '0' and wr = '1' and rd = '0' and cd = '0' then
					nextstate <= writes;
				elsif cs = '0' and wr = '0' and rd = '1' and cd = '0' then
					nextstate <= reads;
				elsif cs = '0' and wr = '1' and rd = '0' and cd = '1' then
					nextstate <= status;
				else 
					nextstate <= tristate;
				end if;
		end case;					   
	end process;

	process ( reset, clk )
	begin
		if reset = '1' then
			currstate <= resets;
		elsif clk = '1' and clk'event then
			currstate <= nextstate;
		end if;
	end process;

	process ( reset, clk )
	begin
		if reset = '1' then
			mireg <= "00000000";
		elsif clk = '1' and clk'event then
			if currstate = modes then
				mireg <= drd;
			end if;
		end if;
	end process;

	process ( reset, clk )
	begin
		if reset = '1' then
			syn1reg <= "00000000";
		elsif clk = '1' and clk'event then
			if currstate = syn1s then
				syn1reg <= drd;
			end if;
		end if;
	end process;

	process ( reset, clk )
	begin
		if reset = '1' then
			syn2reg <= "00000000";
		elsif clk = '1' and clk'event then
			if currstate = syn2s then
				syn2reg <= drd;
			end if;
		end if;
	end process;

	process ( reset, clk )
	begin
		if reset = '1' then
			cireg <= "00010000";
		elsif clk = '1' and clk'event then
			if currstate = commands then
				cireg <= drd;
			end if;
		end if;
	end process;

	process ( reset, clk )
	begin
		if reset = '1' then
			holdreg <= "00000000";
		elsif clk = '1' and clk'event then
			if cs = '0' and wr = '0' and rd = '1' and cd = '0' then
				holdreg <= drd;
			end if;
		end if;
	end process;
			 
	process ( reset, clk )
	begin			 
		if reset = '1' then
			statusreg <= "00000101";
		elsif clk = '1' and clk'event then
			if cs = '0' and wr = '0' and rd = '1' and cd = '0' then
				hold_cts <= not cts;
				statusreg(0) <= '0';
			elsif holdreg_emp = '1' then
				statusreg(0) <= '1';
			end if;

			if rxrdy_status = '1' then
				statusreg(1) <= '1';
			else
				statusreg(1) <= '0';
			end if;

			if txe_status = '1' then
				statusreg(2) <= '1';
			else
				statusreg(2) <= '0'; 
			end if;

			if parity_error = '1' then
				statusreg(3) <= '1';
			else
				statusreg(3) <= '0';
			end if;		   

			if overrun_error = '1' then
				statusreg(4) <= '1';
			else
				statusreg(4) <= '0';
			end if;	 

			if framing_error = '1' then
				statusreg(5) <= '1';
			else
				statusreg(5) <= '0';
			end if;		   

			if syndet_status = '1' then
				statusreg(6) <= '1';
			else
				statusreg(6) <= '0';
			end if;

			statusreg(7) <= not dsr; 
		end if;
	end process;  
	
	process( reset, clk )
	begin
		if reset = '1' then
			en <= '0';
			dwr <= "ZZZZZZZZ";
		elsif clk = '1' and clk'event then
			if cs = '0' and wr = '1' and rd = '0' and cd = '1' then	
				en <= '1';
				dwr <= statusreg;
			elsif cs = '0' and wr = '1' and rd = '0' and cd = '0' then
				en <= '1';
				dwr <= writereg;  
			else		  
				en <= '0';
				dwr <= "ZZZZZZZZ";
			end if;
		end if;
	end process;	 
		
	process( reset, clk )
	begin
		if reset = '1' then
			status_read <= '0';
			data_read <= '0';
		elsif clk = '1' and clk'event then
			if cs = '0' and wr = '1' and rd = '0' and cd = '1' then
				status_read <= '1';
			else
				status_read <= '0';
			end if;
			if cs = '0' and wr = '1' and rd = '0' and cd = '0' then
				data_read <= '1';
			else
				data_read <= '0';
			end if;
		end if;
	end process;
				
end rwc_arc;