stopwatch.v

来自「基于fpga的停表设计vudl编写」· Verilog 代码 · 共 107 行

module stopwatch(	clk,
					rst,
					ms,
					ss,
					mm,
					hh
					);
input clk,rst;
output[6:0] ms,ss,mm;
output[4:0] hh;
reg[6:0] ms,ss,mm,ms_count,ss_count,mm_count;
reg[4:0] hh,hh_count;
reg[5:0] state;
reg[3:0] clk_count;

parameter	MS_NUM	=	100,
			SS_NUM	= 	60,
			MM_NUM	=	60,
			HH_NUM	=	24,
			CLK_NUM	=	10;

parameter	IDLE	=	6'B00_0010,
			MS		=	6'B00_0001,
			SS		=	6'B00_0100,
			MM		=	6'B00_1000,
			HH		=	6'B01_0000,
			CLK		=	6'B10_0000;
			
always @ (posedge clk,posedge rst)
begin
	if (rst)
		begin
			ms <= 1'b0;
			ss <= 1'b0;
			mm <= 1'b0;
			hh <= 1'b0;
			ms_count <= 1'b0;
			ss_count <= 1'b0;
			mm_count <= 1'b0;
			hh_count <= 1'b0;
			clk_count <= 1'b0;
			state <= IDLE;
		end
	else
		begin
			case (state)
				IDLE:	begin
							ms <= 1'b0;
							ss <= 1'b0;
							mm <= 1'b0;
							hh <= 1'b0;
							ms_count <= 1'b0;
							ss_count <= 1'b0;
							mm_count <= 1'b0;
							hh_count <= 1'b0;
							clk_count <= 1'b0;
							state <= CLK;
				end
				CLK:	begin
							clk_count <= clk_count + 1'b1;
							if (clk_count == CLK_NUM)
								begin
									state <= MS;
									clk_count <= 1'b0;
								end
							else state <= CLK;
						end
				MS:		begin
							ms <= ms + 1'b1;
							if (ms == MS_NUM)
								begin
									state <= SS;
									ms <= 1'b0;
								end
							else state <= CLK;
						end
				SS:		begin
							ss <= ss + 1'b1;
							if (ss == SS_NUM)
								begin
									state <= MM;
									ss <= 1'b0;
								end
							else state <= CLK;
						end
				MM:		begin
							mm <= mm + 1'b1;
							if (mm == MM_NUM)
								begin
									state <= HH;
									mm <= 1'b0;
								end
							else state <= CLK;
						end
				HH:		begin
							hh <= hh + 1'b1;
							if (hh == HH_NUM)
								begin
									state <= IDLE;
									hh <= 1'b0;
								end
							else state <= CLK;
				end
			endcase
		end
end 			
endmodule