stopwatch_tb.v

来自「基于fpga的停表设计vudl编写」· Verilog 代码 · 共 26 行

`timescale 100us/10us
module stopwatch_tb;
reg clk,rst;
wire[6:0] ss,mm,ms;
wire[4:0] hh;

always #5 clk = ~clk;

initial  begin
			clk = 0;			
end

initial begin
			rst = 0;
			#1 rst = 1;
			#7 rst = 0;
end

stopwatch U1(	.clk(clk),
				.rst(rst),
				.ms(ms),
				.ss(ss),
				.mm(mm),
				.hh(hh)
				);
endmodule