make_verilog

来自「8051 core writen in VHDL, fully functio」· 代码 · 共 33 行

verilog 						\
../../../bench/verilog/oc8051_tb.v			\
../../../bench/verilog/oc8051_xram.v 			\
../../../bench/verilog/oc8051_uart_test.v 		\
../../../bench/verilog/oc8051_xrom.v 			\
../../../rtl/verilog/oc8051_top.v			\
../../../rtl/verilog/oc8051_alu_src_sel.v		\
../../../rtl/verilog/oc8051_alu.v 			\
../../../rtl/verilog/oc8051_decoder.v 			\
../../../rtl/verilog/oc8051_divide.v 			\
../../../rtl/verilog/oc8051_multiply.v 			\
../../../rtl/verilog/oc8051_memory_interface.v 		\
../../../rtl/verilog/oc8051_ram_top.v			\
../../../rtl/verilog/oc8051_acc.v 			\
../../../rtl/verilog/oc8051_comp.v 			\
../../../rtl/verilog/oc8051_sp.v 			\
../../../rtl/verilog/oc8051_dptr.v 			\
../../../rtl/verilog/oc8051_cy_select.v 		\
../../../rtl/verilog/oc8051_psw.v 			\
../../../rtl/verilog/oc8051_indi_addr.v 		\
../../../rtl/verilog/oc8051_ports.v 			\
../../../rtl/verilog/oc8051_b_register.v 		\
../../../rtl/verilog/oc8051_uart.v 			\
../../../rtl/verilog/oc8051_int.v 			\
../../../rtl/verilog/oc8051_tc.v 			\
../../../rtl/verilog/oc8051_tc2.v 			\
../../../rtl/verilog/oc8051_icache.v 			\
../../../rtl/verilog/oc8051_wb_iinterface.v 		\
../../../rtl/verilog/oc8051_sfr.v			\
../../../rtl/verilog/oc8051_rom.v 			\
../../../rtl/verilog/oc8051_cache_ram.v			\
../../../../common/generic_memories/rtl/verilog/generic_dpram.v