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📄 std_2s60.ptf

📁 Vga Controller source code for Altera FPGA
💻 PTF
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                  INCLK0_INPUT_FREQUENCY = "20000";
                  SPREAD_FREQUENCY = "0";
               }
               STRING 
               {
                  BANDWIDTH_TYPE = "AUTO";
                  CLK0_PHASE_SHIFT = "0";
                  CLK1_PHASE_SHIFT = "-3500";
                  COMPENSATE_CLOCK = "CLK0";
                  INTENDED_DEVICE_FAMILY = "Stratix II";
                  LPM_TYPE = "altpll";
                  OPERATION_MODE = "NORMAL";
                  PLL_TYPE = "AUTO";
               }
            }
            GEN_FILE 
            {
               TYPE_NORMAL 
               {
                  FALSE 
                  {
                     name1 = ".inc";
                     name2 = ".cmp";
                     name4 = "_inst.v";
                     name7 = "_wave*.jpg";
                  }
                  TRUE 
                  {
                     name0 = ".v";
                     name3 = ".bsf";
                     name5 = "_bb.v";
                     name6 = "_waveforms.html";
                  }
               }
            }
            LIBRARY = "altera_mf altera_mf.altera_mf_components.all";
            PRIVATE 
            {
               NUMERIC 
               {
                  DIV_FACTOR0 = "1";
                  DIV_FACTOR1 = "1";
                  GLOCK_COUNTER_EDIT = "1048575";
                  LVDS_MODE_DATA_RATE_DIRTY = "0";
                  MULT_FACTOR0 = "1";
                  MULT_FACTOR1 = "1";
                  PLL_AUTOPLL_CHECK = "1";
                  PLL_ENHPLL_CHECK = "0";
                  PLL_FASTPLL_CHECK = "0";
                  PLL_LVDS_PLL_CHECK = "0";
                  PLL_TARGET_HARCOPY_CHECK = "0";
                  SWITCHOVER_COUNT_EDIT = "1";
               }
               STRING 
               {
                  ACTIVECLK_CHECK = "0";
                  BANDWIDTH = "1.000";
                  BANDWIDTH_FEATURE_ENABLED = "1";
                  BANDWIDTH_FREQ_UNIT = "MHz";
                  BANDWIDTH_PRESET = "Low";
                  BANDWIDTH_USE_AUTO = "1";
                  BANDWIDTH_USE_CUSTOM = "0";
                  BANDWIDTH_USE_PRESET = "0";
                  CLKBAD_SWITCHOVER_CHECK = "0";
                  CLKLOSS_CHECK = "0";
                  CLKSWITCH_CHECK = "0";
                  CNX_NO_COMPENSATE_RADIO = "0";
                  CREATE_CLKBAD_CHECK = "0";
                  CREATE_INCLK1_CHECK = "0";
                  CUR_DEDICATED_CLK = "c0";
                  CUR_FBIN_CLK = "e0";
                  DEVICE_SPEED_GRADE = "Any";
                  DEV_FAMILY = "Stratix II";
                  DUTY_CYCLE0 = "50.00000000";
                  DUTY_CYCLE1 = "50.00000000";
                  EXT_FEEDBACK_RADIO = "0";
                  GLOCKED_COUNTER_EDIT_CHANGED = "1";
                  GLOCKED_FEATURE_ENABLED = "1";
                  GLOCKED_MODE_CHECK = "0";
                  HAS_MANUAL_SWITCHOVER = "1";
                  INCLK0_FREQ_EDIT = "50.000";
                  INCLK0_FREQ_UNIT_COMBO = "MHz";
                  INCLK1_FREQ_EDIT = "100.000";
                  INCLK1_FREQ_EDIT_CHANGED = "1";
                  INCLK1_FREQ_UNIT_CHANGED = "1";
                  INCLK1_FREQ_UNIT_COMBO = "MHz";
                  INT_FEEDBACK__MODE_RADIO = "1";
                  LOCKED_OUTPUT_CHECK = "0";
                  LONG_SCAN_RADIO = "1";
                  LVDS_MODE_DATA_RATE = "150.000";
                  LVDS_PHASE_SHIFT_UNIT0 = "deg";
                  LVDS_PHASE_SHIFT_UNIT1 = "ps";
                  NORMAL_MODE_RADIO = "1";
                  OUTPUT_FREQ0 = "65.000";
                  OUTPUT_FREQ1 = "65.000";
                  OUTPUT_FREQ_MODE0 = "1";
                  OUTPUT_FREQ_MODE1 = "1";
                  OUTPUT_FREQ_UNIT0 = "MHz";
                  OUTPUT_FREQ_UNIT1 = "MHz";
                  PHASE_SHIFT0 = "0.00000000";
                  PHASE_SHIFT1 = "-3.50000000";
                  PHASE_SHIFT_UNIT0 = "deg";
                  PHASE_SHIFT_UNIT1 = "ns";
                  PLL_ADVANCED_PARAM_CHECK = "0";
                  PLL_ARESET_CHECK = "0";
                  PLL_ENA_CHECK = "0";
                  PLL_PFDENA_CHECK = "0";
                  PRIMARY_CLK_COMBO = "inclk0";
                  SACN_INPUTS_CHECK = "0";
                  SCAN_FEATURE_ENABLED = "1";
                  SHORT_SCAN_RADIO = "0";
                  SPREAD_FEATURE_ENABLED = "1";
                  SPREAD_FREQ = "50.000";
                  SPREAD_FREQ_UNIT = "KHz";
                  SPREAD_PERCENT = "0.500";
                  SPREAD_USE = "0";
                  SRC_SYNCH_COMP_RADIO = "0";
                  STICKY_CLK0 = "1";
                  STICKY_CLK1 = "1";
                  SWITCHOVER_FEATURE_ENABLED = "1";
                  USE_CLK0 = "1";
                  USE_CLK1 = "1";
                  ZERO_DELAY_RADIO = "0";
               }
            }
            USED_PORT 
            {
               c0 
               {
                  VALUE_0 = "0";
                  VALUE_1 = "0";
                  VALUE_2 = "0";
                  VALUE_3 = "0";
                  VALUE_4 = "OUTPUT";
                  VALUE_5 = "VCC";
               }
               c1 
               {
                  VALUE_0 = "0";
                  VALUE_1 = "0";
                  VALUE_2 = "0";
                  VALUE_3 = "0";
                  VALUE_4 = "OUTPUT";
                  VALUE_5 = "VCC";
               }
            }
         }
      }
      PORT_WIRING 
      {
         PORT areset
         {
            Is_Enabled = "0";
            direction = "input";
            width = "1";
         }
         PORT locked
         {
            Is_Enabled = "0";
            direction = "output";
            width = "1";
         }
         PORT pfdena
         {
            Is_Enabled = "0";
            direction = "input";
            width = "1";
         }
         PORT pllena
         {
            Is_Enabled = "0";
            direction = "input";
            width = "1";
         }
      }
   }
   MODULE cpu
   {
      class = "altera_nios2";
      class_version = "5.1";
      iss_model_name = "altera_nios2";
      HDL_INFO 
      {
         PLI_Files = "";
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/cpu_test_bench.v, __PROJECT_DIRECTORY__/cpu_mult_cell.v, __PROJECT_DIRECTORY__/cpu_jtag_debug_module.v, __PROJECT_DIRECTORY__/cpu_jtag_debug_module_wrapper.v, __PROJECT_DIRECTORY__/cpu.v";
         Synthesis_Only_Files = "";
      }
      MASTER instruction_master
      {
         PORT_WIRING 
         {
            PORT i_address
            {
               direction = "output";
               type = "address";
               width = "26";
               Is_Enabled = "1";
            }
            PORT i_read
            {
               direction = "output";
               type = "read";
               width = "1";
               Is_Enabled = "1";
            }
            PORT i_readdata
            {
               direction = "input";
               type = "readdata";
               width = "32";
               Is_Enabled = "1";
            }
            PORT i_readdatavalid
            {
               direction = "input";
               type = "readdatavalid";
               width = "1";
               Is_Enabled = "1";
            }
            PORT i_waitrequest
            {
               direction = "input";
               type = "waitrequest";
               width = "1";
               Is_Enabled = "1";
            }
            PORT jtag_debug_trigout
            {
               width = "1";
               direction = "output";
               Is_Enabled = "0";
            }
            PORT jtag_debug_offchip_trace_clk
            {
               width = "1";
               direction = "output";
               Is_Enabled = "0";
            }
            PORT jtag_debug_offchip_trace_data
            {
               width = "18";
               direction = "output";
               Is_Enabled = "0";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Instruction_Master = "1";
            Has_IRQ = "0";
            Irq_Scheme = "individual_requests";
            Interrupt_Range = "0-0";
            Is_Enabled = "1";
            Maximum_Burst_Size = "1";
            Burst_On_Burst_Boundaries_Only = "";
            Linewrap_Bursts = "";
            Interleave_Bursts = "";
            Is_Readable = "1";
            Is_Writeable = "0";
            Address_Group = "0";
         }
      }
      MASTER data_master
      {
         PORT_WIRING 
         {
            PORT clk
            {
               direction = "input";
               type = "clk";
               width = "1";
               Is_Enabled = "1";
            }
            PORT d_address
            {
               direction = "output";
               type = "address";
               width = "26";
               Is_Enabled = "1";
            }
            PORT d_byteenable
            {
               direction = "output";
               type = "byteenable";
               width = "4";
               Is_Enabled = "1";
            }
            PORT d_irq
            {
               direction = "input";
               type = "irq";
               width = "32";
               Is_Enabled = "1";
            }
            PORT d_read
            {
               direction = "output";
               type = "read";
               width = "1";
               Is_Enabled = "1";
            }
            PORT d_readdata
            {
               direction = "input";
               type = "readdata";
               width = "32";
               Is_Enabled = "1";
            }
            PORT d_waitrequest
            {
               direction = "input";
               type = "waitrequest";
               width = "1";
               Is_Enabled = "1";
            }
            PORT d_write
            {
               direction = "output";
               type = "write";
               width = "1";
               Is_Enabled = "1";
            }
            PORT d_writedata
            {
               direction = "output";
               type = "writedata";
               width = "32";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_debugaccess_to_roms
            {
               direction = "output";
               type = "debugaccess";
               width = "1";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "1";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Data_Master = "1";
            Has_IRQ = "1";
            Irq_Scheme = "individual_requests";
            Interrupt_Range = "0-31";
            Is_Enabled = "1";
            Maximum_Burst_Size = "1";
            Burst_On_Burst_Boundaries_Only = "";
            Is_Readable = "1";
            Is_Writeable = "1";
            Address_Group = "0";
            Adapts_To = "";
         }
      }
      SLAVE jtag_debug_module
      {
         PORT_WIRING 
         {
            PORT jtag_debug_module_address
            {
               direction = "input";
               type = "address";
               width = "9";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_begintransfer
            {
               direction = "input";
               type = "begintransfer";
               width = "1";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_clk
            {
               direction = "input";
               type = "clk";
               width = "1";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_debugaccess
            {
               direction = "input";
               type = "debugaccess";
               width = "1";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_readdata
            {
               direction = "output";
               type = "readdata";
               width = "32";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_reset
            {
               direction = "input";
               type = "reset";
               width = "1";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_resetrequest
            {
               direction = "output";
               type = "resetrequest";
               width = "1";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_select
            {
               direction = "input";
               type = "chipselect";
               width = "1";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_write
            {
               direction = "input";
               type = "write";
               width = "1";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_writedata

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