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📄 std_2s60.ptf

📁 Vga Controller source code for Altera FPGA
💻 PTF
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               DIVIDE_BY = "50";
               DUTY_CYCLE = "50";
               MULTIPLY_BY = "93";
               PHASE_SHIFT = "-3500";
               clk_index = "1";
               clock_freq = "93000000";
               clock_unit = "MHz";
               type = "out_clk";
            }
         }
         CNX_INFO 
         {
            CONSTANT 
            {
               NUMERIC 
               {
                  CLK0_DIVIDE_BY = "50";
                  CLK0_DUTY_CYCLE = "50";
                  CLK0_MULTIPLY_BY = "93";
                  CLK1_DIVIDE_BY = "50";
                  CLK1_DUTY_CYCLE = "50";
                  CLK1_MULTIPLY_BY = "93";
                  INCLK0_INPUT_FREQUENCY = "20000";
                  SPREAD_FREQUENCY = "0";
               }
               STRING 
               {
                  BANDWIDTH_TYPE = "AUTO";
                  CLK0_PHASE_SHIFT = "0";
                  CLK1_PHASE_SHIFT = "-3500";
                  COMPENSATE_CLOCK = "CLK0";
                  INTENDED_DEVICE_FAMILY = "Stratix II";
                  LPM_TYPE = "altpll";
                  OPERATION_MODE = "NORMAL";
                  PLL_TYPE = "ENHANCED";
               }
            }
            GEN_FILE 
            {
               TYPE_NORMAL 
               {
                  FALSE 
                  {
                     name2 = ".cmp";
                     name1 = ".inc";
                     name4 = "_inst.v";
                     name7 = "_wave*.jpg";
                  }
                  TRUE 
                  {
                     name6 = "_waveforms.html";
                     name0 = ".v";
                     name3 = ".bsf";
                     name5 = "_bb.v";
                  }
               }
            }
            LIBRARY = "altera_mf altera_mf.altera_mf_components.all";
            PRIVATE 
            {
               NUMERIC 
               {
                  DIV_FACTOR0 = "1";
                  DIV_FACTOR1 = "1";
                  GLOCK_COUNTER_EDIT = "1048575";
                  LVDS_MODE_DATA_RATE_DIRTY = "0";
                  MULT_FACTOR0 = "1";
                  MULT_FACTOR1 = "1";
                  PLL_AUTOPLL_CHECK = "0";
                  PLL_ENHPLL_CHECK = "1";
                  PLL_FASTPLL_CHECK = "0";
                  PLL_LVDS_PLL_CHECK = "0";
                  SWITCHOVER_COUNT_EDIT = "1";
                  PLL_TARGET_HARCOPY_CHECK = "0";
               }
               STRING 
               {
                  ACTIVECLK_CHECK = "0";
                  BANDWIDTH = "1.000";
                  BANDWIDTH_FEATURE_ENABLED = "1";
                  BANDWIDTH_FREQ_UNIT = "MHz";
                  BANDWIDTH_PRESET = "Low";
                  BANDWIDTH_USE_AUTO = "1";
                  BANDWIDTH_USE_CUSTOM = "0";
                  BANDWIDTH_USE_PRESET = "0";
                  CLKBAD_SWITCHOVER_CHECK = "0";
                  CLKLOSS_CHECK = "0";
                  CLKSWITCH_CHECK = "0";
                  CNX_NO_COMPENSATE_RADIO = "0";
                  CREATE_CLKBAD_CHECK = "0";
                  CREATE_INCLK1_CHECK = "0";
                  CUR_DEDICATED_CLK = "c0";
                  CUR_FBIN_CLK = "e0";
                  DEVICE_SPEED_GRADE = "Any";
                  DEV_FAMILY = "Stratix II";
                  DUTY_CYCLE0 = "50.00000000";
                  DUTY_CYCLE1 = "50.00000000";
                  EXT_FEEDBACK_RADIO = "0";
                  GLOCKED_COUNTER_EDIT_CHANGED = "1";
                  GLOCKED_FEATURE_ENABLED = "1";
                  GLOCKED_MODE_CHECK = "0";
                  HAS_MANUAL_SWITCHOVER = "1";
                  INCLK0_FREQ_EDIT = "50.000";
                  INCLK0_FREQ_UNIT_COMBO = "MHz";
                  INCLK1_FREQ_EDIT = "100.000";
                  INCLK1_FREQ_EDIT_CHANGED = "1";
                  INCLK1_FREQ_UNIT_CHANGED = "1";
                  INCLK1_FREQ_UNIT_COMBO = "MHz";
                  INT_FEEDBACK__MODE_RADIO = "1";
                  LOCKED_OUTPUT_CHECK = "0";
                  LONG_SCAN_RADIO = "1";
                  LVDS_MODE_DATA_RATE = "Not Available";
                  LVDS_PHASE_SHIFT_UNIT0 = "deg";
                  LVDS_PHASE_SHIFT_UNIT1 = "ps";
                  NORMAL_MODE_RADIO = "1";
                  OUTPUT_FREQ0 = "93.000";
                  OUTPUT_FREQ1 = "93.000";
                  OUTPUT_FREQ_MODE0 = "1";
                  OUTPUT_FREQ_MODE1 = "1";
                  OUTPUT_FREQ_UNIT0 = "MHz";
                  OUTPUT_FREQ_UNIT1 = "MHz";
                  PHASE_SHIFT0 = "0.00000000";
                  PHASE_SHIFT1 = "-3.50000000";
                  PHASE_SHIFT_UNIT0 = "deg";
                  PHASE_SHIFT_UNIT1 = "ns";
                  PLL_ADVANCED_PARAM_CHECK = "0";
                  PLL_ARESET_CHECK = "0";
                  PLL_ENA_CHECK = "0";
                  PLL_PFDENA_CHECK = "0";
                  PRIMARY_CLK_COMBO = "inclk0";
                  SACN_INPUTS_CHECK = "0";
                  SCAN_FEATURE_ENABLED = "1";
                  SHORT_SCAN_RADIO = "0";
                  SPREAD_FEATURE_ENABLED = "1";
                  SPREAD_FREQ = "50.000";
                  SPREAD_FREQ_UNIT = "KHz";
                  SPREAD_PERCENT = "0.500";
                  SPREAD_USE = "0";
                  SRC_SYNCH_COMP_RADIO = "0";
                  STICKY_CLK0 = "1";
                  STICKY_CLK1 = "1";
                  SWITCHOVER_FEATURE_ENABLED = "1";
                  USE_CLK0 = "1";
                  USE_CLK1 = "1";
                  ZERO_DELAY_RADIO = "0";
               }
            }
            USED_PORT 
            {
               c0 
               {
                  VALUE_0 = "0";
                  VALUE_1 = "0";
                  VALUE_2 = "0";
                  VALUE_3 = "0";
                  VALUE_4 = "OUTPUT";
                  VALUE_5 = "VCC";
               }
               c1 
               {
                  VALUE_0 = "0";
                  VALUE_1 = "0";
                  VALUE_2 = "0";
                  VALUE_3 = "0";
                  VALUE_4 = "OUTPUT";
                  VALUE_5 = "VCC";
               }
            }
         }
      }
      PORT_WIRING 
      {
         PORT areset
         {
            Is_Enabled = "0";
            direction = "input";
            width = "1";
         }
         PORT locked
         {
            Is_Enabled = "0";
            direction = "output";
            width = "1";
         }
         PORT pfdena
         {
            Is_Enabled = "0";
            direction = "input";
            width = "1";
         }
         PORT pllena
         {
            Is_Enabled = "0";
            direction = "input";
            width = "1";
         }
      }
   }
   MODULE vga_pll
   {
      class = "altera_avalon_pll";
      class_version = "5.1";
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/vga_pll.v, __PROJECT_DIRECTORY__/altpllvga_pll.v";
         Synthesis_Only_Files = "";
      }
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Default_Module_Name = "pll";
         Clock_Source = "clk";
         Required_Device_Family = "STRATIX,STRATIXGX,STRATIXII,STRATIXIIGX,CYCLONE,CYCLONEII";
         Top_Level_Ports_Are_Enumerated = "1";
         View 
         {
            Settings_Summary = " Avalon PLL: <br>         input clock configured: <b>sys_clk</b>        ";
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
      }
      SLAVE s1
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Address_Width = "3";
            Data_Width = "16";
            Has_IRQ = "0";
            Read_Wait_States = "1";
            Write_Wait_States = "0";
            Date_Modified = "";
            Is_Enabled = "1";
            Instantiate_In_System_Module = "1";
            Requires_Internal_Clock_Promotion = "Yes";
            Is_Clock_Source = "1";
            Base_Address = "0x021208E0";
            Address_Group = "0";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
            Is_Base_Locked = "0";
         }
         PORT_WIRING 
         {
            PORT address
            {
               direction = "input";
               type = "address";
               width = "3";
               Is_Enabled = "1";
            }
            PORT clk
            {
               direction = "input";
               type = "clk";
               width = "1";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               direction = "input";
               type = "reset_n";
               width = "1";
               Is_Enabled = "1";
            }
            PORT c0
            {
               Is_Enabled = "1";
               direction = "output";
               type = "out_clk";
               width = "1";
            }
            PORT c1
            {
               Is_Enabled = "1";
               direction = "output";
               type = "out_clk";
               width = "1";
            }
            PORT chipselect
            {
               Is_Enabled = "1";
               direction = "input";
               type = "chipselect";
               width = "1";
            }
            PORT read
            {
               Is_Enabled = "1";
               direction = "input";
               type = "read";
               width = "1";
            }
            PORT readdata
            {
               Is_Enabled = "1";
               direction = "output";
               type = "readdata";
               width = "16";
            }
            PORT resetrequest
            {
               Is_Enabled = "1";
               direction = "output";
               type = "resetrequest";
               width = "1";
            }
            PORT write
            {
               Is_Enabled = "1";
               direction = "input";
               type = "write";
               width = "1";
            }
            PORT writedata
            {
               Is_Enabled = "1";
               direction = "input";
               type = "writedata";
               width = "16";
            }
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         locked = "None";
         areset = "None";
         pllena = "None";
         pfdena = "None";
         Config_Done = "1";
         UI_CONTROL 
         {
            areset_port_exist = "0";
            pllena_port_exist = "0";
            pfdena_port_exist = "0";
            locked_port_exist = "0";
         }
         ALTPLL_PORTS 
         {
            PORT c0
            {
               Is_Enabled = "1";
               direction = "output";
               type = "out_clk";
               width = "1";
            }
            PORT c1
            {
               Is_Enabled = "1";
               direction = "output";
               type = "out_clk";
               width = "1";
            }
            PORT inclk0
            {
               Is_Enabled = "1";
               direction = "input";
               type = "in_clk";
               width = "1";
            }
         }
         CLOCK_INFO 
         {
            CLOCK inclk0
            {
               clock_freq = "50000000";
               clock_unit = "MHz";
               type = "in_clk";
            }
            NUMBER_OF_INPUT_CLOCKS = "1";
            NUMBER_OF_OUTPUT_CLOCKS = "2";
            RECONFIG_ENABLED = "0";
            USED_OUTPUT_CLOCKS 
            {
               INDEX_0 = "0";
               INDEX_1 = "1";
            }
         }
         CLOCK_SOURCES 
         {
            CLOCK c0
            {
               DIVIDE_BY = "10";
               DUTY_CYCLE = "50";
               MULTIPLY_BY = "13";
               PHASE_SHIFT = "0";
               clk_index = "0";
               clock_freq = "65000000";
               clock_unit = "MHz";
               type = "out_clk";
            }
            CLOCK c1
            {
               DIVIDE_BY = "10";
               DUTY_CYCLE = "50";
               MULTIPLY_BY = "13";
               PHASE_SHIFT = "-3500";
               clk_index = "1";
               clock_freq = "65000000";
               clock_unit = "MHz";
               type = "out_clk";
            }
         }
         CNX_INFO 
         {
            CONSTANT 
            {
               NUMERIC 
               {
                  CLK0_DIVIDE_BY = "10";
                  CLK0_DUTY_CYCLE = "50";
                  CLK0_MULTIPLY_BY = "13";
                  CLK1_DIVIDE_BY = "10";
                  CLK1_DUTY_CYCLE = "50";
                  CLK1_MULTIPLY_BY = "13";

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