std_2s60.ptf

Vga Controller source code for Altera FPGA

SYSTEM std_2s60
{
   System_Wizard_Version = "5.10";
   System_Wizard_Build = "174";
   WIZARD_SCRIPT_ARGUMENTS 
   {
      device_family = "STRATIXII";
      clock_freq = "93000000";
      generate_hdl = "1";
      generate_sdk = "0";
      do_build_sim = "0";
      hdl_language = "verilog";
      view_master_columns = "1";
      view_master_priorities = "1";
      board_class = "nios_ep2s60_with_lancelot";
      name_column_width = "217";
      desc_column_width = "217";
      bustype_column_width = "0";
      base_column_width = "75";
      end_column_width = "75";
      view_frame_window = "1:1:1022:706";
      do_log_history = "0";
      device_family_id = "STRATIXII";
      CLOCKS 
      {
         CLOCK sys_clk
         {
            Is_Clock_Source = "0";
            frequency = "93000000";
            source = "sys_pll_c0";
            display_name = "sys_clk";
            BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
            {
               component_pin = "use_quartus_pin_assignment";
               pin_assignment = "";
            }
            BOARD_COMPONENT nios_ep2s60_with_lancelot
            {
               component_pin = "use_quartus_pin_assignment";
               pin_assignment = "";
            }
         }
         CLOCK sys_pll_c1
         {
            frequency = "93000000";
            source = "";
            Is_Clock_Source = "1";
            display_name = "c1 from sys_pll";
            pipeline = "0";
            BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
            {
               component_pin = "use_quartus_pin_assignment";
               pin_assignment = "";
            }
         }
         CLOCK sys_pll_c0
         {
            frequency = "93000000";
            source = "";
            Is_Clock_Source = "1";
            display_name = "c0 from sys_pll";
            pipeline = "0";
            BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
            {
               component_pin = "use_quartus_pin_assignment";
               pin_assignment = "";
            }
         }
         CLOCK sdram_clk_out
         {
            frequency = "93000000";
            source = "sys_pll_c1";
            Is_Clock_Source = "0";
            display_name = "sdram_clk_out";
            pipeline = "0";
            BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
            {
               component_pin = "use_quartus_pin_assignment";
               pin_assignment = "";
            }
            BOARD_COMPONENT nios_ep2s60_with_lancelot
            {
               component_pin = "use_quartus_pin_assignment";
               pin_assignment = "";
            }
         }
         CLOCK clk
         {
            frequency = "50000000";
            source = "External";
            Is_Clock_Source = "0";
            display_name = "clk";
            pipeline = "0";
            BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
            {
               component_pin = "use_quartus_pin_assignment";
               pin_assignment = "";
            }
            BOARD_COMPONENT nios_ep2s60_with_lancelot
            {
               component_pin = "use_quartus_pin_assignment";
               pin_assignment = "";
            }
         }
         CLOCK vga_pll_c0
         {
            frequency = "65000000";
            source = "";
            Is_Clock_Source = "1";
            display_name = "c0 from vga_pll";
            pipeline = "0";
         }
         CLOCK vga_int_clk
         {
            frequency = "65000000";
            source = "vga_pll_c0";
            Is_Clock_Source = "0";
            display_name = "vga_int_clk";
            pipeline = "0";
            BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
            {
               pin_assignment = "";
               component_pin = "use_quartus_pin_assignment";
            }
            BOARD_COMPONENT nios_ep2s60_with_lancelot
            {
               component_pin = "use_quartus_pin_assignment";
               pin_assignment = "";
            }
         }
         CLOCK vga_pll_c1
         {
            frequency = "65000000";
            source = "";
            Is_Clock_Source = "1";
            display_name = "c1 from vga_pll";
            pipeline = "0";
         }
         CLOCK vga_ext_clk
         {
            frequency = "65000000";
            source = "vga_pll_c1";
            Is_Clock_Source = "0";
            display_name = "vga_ext_clk";
            pipeline = "0";
            BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
            {
               pin_assignment = "";
               component_pin = "use_quartus_pin_assignment";
            }
            BOARD_COMPONENT nios_ep2s60_with_lancelot
            {
               component_pin = "use_quartus_pin_assignment";
               pin_assignment = "";
            }
         }
      }
      clock_column_width = "68";
      hardcopy_compatible = "0";
      RESETS 
      {
         RESET reset
         {
            BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
            {
               component_pin = "use_quartus_pin_assignment";
               pin_assignment = "";
            }
         }
         RESET reset_n
         {
            BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
            {
               pin_assignment = "";
               component_pin = "use_quartus_pin_assignment";
            }
            BOARD_COMPONENT nios_ep2s60_with_lancelot
            {
               component_pin = "use_quartus_pin_assignment";
               pin_assignment = "";
            }
         }
      }
      BOARD_INFO 
      {
         JTAG_device_index = "1";
         REFDES U5
         {
            base = "0x01000000";
         }
         altera_avalon_cfi_flash 
         {
            reference_designators = "U5";
         }
         class = "nios_ep2s60_with_lancelot";
         class_version = "5.1";
         device_family = "STRATIXII";
         quartus_pgm_file = "system/altera_nios_dev_board_stratix_2s60.sof";
         quartus_project_file = "system/altera_nios_dev_board_stratix_2s60.qpf";
         reference_designators = "U5";
         sopc_system_file = "system/altera_nios_dev_board_stratix_2s60.ptf";
         altera_avalon_epcs_flash_controller 
         {
            reference_designators = "";
         }
         initial_system_file = "";
         CONFIGURATION user
         {
            reference_designator = "U5";
            offset = "0x800000";
            menu_position = "0";
         }
         CONFIGURATION factory
         {
            reference_designator = "U5";
            offset = "0xC00000";
            menu_position = "1";
         }
      }
   }
   MODULE sys_pll
   {
      class = "altera_avalon_pll";
      class_version = "5.1";
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sys_pll.v, __PROJECT_DIRECTORY__/altpllsys_pll.v";
         Synthesis_Only_Files = "";
      }
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Default_Module_Name = "pll";
         Clock_Source = "clk";
         Required_Device_Family = "STRATIX,STRATIXGX,STRATIXII,STRATIXIIGX,CYCLONE,CYCLONEII";
         Top_Level_Ports_Are_Enumerated = "1";
         View 
         {
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
            Settings_Summary = " Avalon PLL: <br>
         input clock configured: <b>clk</b>
        ";
         }
      }
      SLAVE s1
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Address_Width = "3";
            Data_Width = "16";
            Has_IRQ = "0";
            Read_Wait_States = "1";
            Write_Wait_States = "0";
            Date_Modified = "";
            Is_Enabled = "1";
            Instantiate_In_System_Module = "1";
            Requires_Internal_Clock_Promotion = "Yes";
            Is_Clock_Source = "1";
            Base_Address = "0x021208C0";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
            Address_Group = "0";
            Is_Base_Locked = "0";
         }
         PORT_WIRING 
         {
            PORT address
            {
               direction = "input";
               type = "address";
               width = "3";
               Is_Enabled = "1";
            }
            PORT clk
            {
               direction = "input";
               type = "clk";
               width = "1";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               direction = "input";
               type = "reset_n";
               width = "1";
               Is_Enabled = "1";
            }
            PORT c0
            {
               Is_Enabled = "1";
               direction = "output";
               type = "out_clk";
               width = "1";
            }
            PORT c1
            {
               Is_Enabled = "1";
               direction = "output";
               type = "out_clk";
               width = "1";
            }
            PORT chipselect
            {
               Is_Enabled = "1";
               direction = "input";
               type = "chipselect";
               width = "1";
            }
            PORT read
            {
               Is_Enabled = "1";
               direction = "input";
               type = "read";
               width = "1";
            }
            PORT readdata
            {
               Is_Enabled = "1";
               direction = "output";
               type = "readdata";
               width = "16";
            }
            PORT resetrequest
            {
               Is_Enabled = "1";
               direction = "output";
               type = "resetrequest";
               width = "1";
            }
            PORT write
            {
               Is_Enabled = "1";
               direction = "input";
               type = "write";
               width = "1";
            }
            PORT writedata
            {
               Is_Enabled = "1";
               direction = "input";
               type = "writedata";
               width = "16";
            }
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         locked = "None";
         areset = "None";
         pllena = "None";
         pfdena = "None";
         Config_Done = "1";
         UI_CONTROL 
         {
            areset_port_exist = "0";
            pllena_port_exist = "0";
            pfdena_port_exist = "0";
            locked_port_exist = "0";
         }
         ALTPLL_PORTS 
         {
            PORT c0
            {
               Is_Enabled = "1";
               direction = "output";
               type = "out_clk";
               width = "1";
            }
            PORT c1
            {
               Is_Enabled = "1";
               direction = "output";
               type = "out_clk";
               width = "1";
            }
            PORT inclk0
            {
               Is_Enabled = "1";
               direction = "input";
               type = "in_clk";
               width = "1";
            }
         }
         CLOCK_INFO 
         {
            CLOCK inclk0
            {
               clock_freq = "50000000";
               clock_unit = "MHz";
               type = "in_clk";
            }
            NUMBER_OF_INPUT_CLOCKS = "1";
            NUMBER_OF_OUTPUT_CLOCKS = "2";
            RECONFIG_ENABLED = "0";
            USED_OUTPUT_CLOCKS 
            {
               INDEX_0 = "0";
               INDEX_1 = "1";
            }
         }
         CLOCK_SOURCES 
         {
            CLOCK c0
            {
               DIVIDE_BY = "50";
               DUTY_CYCLE = "50";
               MULTIPLY_BY = "93";
               PHASE_SHIFT = "0";
               clk_index = "0";
               clock_freq = "93000000";
               clock_unit = "MHz";
               type = "out_clk";
            }
            CLOCK c1
            {