cc2420interface.fit.smsg

对cc2420无线模块的接口。接受到的数据都使用双口ROM的方式与后台核心控制部分传送。

    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node fifo_w~0
        Info: Destination node Selector32~9
Info: Automatically promoted node command_end_delay_set_flag 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node command_end_delay~0
        Info: Destination node Selector25~17
Info: Automatically promoted node register_end_delay_set_flag 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node register_end_delay~0
        Info: Destination node Selector30~13
Info: Automatically promoted node fifo_w_end_delay_set_flag 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node fifo_w_end_delay~0
        Info: Destination node Selector33~8
Info: Automatically promoted node register_w_set_flag 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node register_w~0
        Info: Destination node Selector28~13
Info: Automatically promoted node command_w_set_flag 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node command_w~0
        Info: Destination node Selector24~14
Info: Automatically promoted node fifo_r_set_flag1 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node fifo_r_w~0
        Info: Destination node Selector68~10
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
    Extra Info: Packed 10 registers into blocks of type EC
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 61 (unused VREF, 3.30 VCCIO, 14 input, 47 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  39 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  31 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  43 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  40 pins available
        Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  39 pins available
        Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  35 pins available
        Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  40 pins available
        Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  43 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:01
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:03
Info: Estimated most critical path is register to register delay of 18.086 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X33_Y20; Fanout = 29; REG Node = 'fifo_w_delay_count[9]'
    Info: 2: + IC(0.230 ns) + CELL(0.651 ns) = 0.881 ns; Loc. = LAB_X33_Y20; Fanout = 1; COMB Node = 'WideOr47~15074'
    Info: 3: + IC(1.331 ns) + CELL(0.206 ns) = 2.418 ns; Loc. = LAB_X32_Y18; Fanout = 13; COMB Node = 'Equal408~73'
    Info: 4: + IC(1.280 ns) + CELL(0.624 ns) = 4.322 ns; Loc. = LAB_X30_Y19; Fanout = 6; COMB Node = 'Equal413~67'
    Info: 5: + IC(1.331 ns) + CELL(0.206 ns) = 5.859 ns; Loc. = LAB_X29_Y17; Fanout = 5; COMB Node = 'Equal476~82'
    Info: 6: + IC(1.708 ns) + CELL(0.206 ns) = 7.773 ns; Loc. = LAB_X27_Y15; Fanout = 2; COMB Node = 'Equal516~68'
    Info: 7: + IC(2.083 ns) + CELL(0.202 ns) = 10.058 ns; Loc. = LAB_X33_Y16; Fanout = 1; COMB Node = 'ram_addr_buf[12]~3409'
    Info: 8: + IC(0.160 ns) + CELL(0.647 ns) = 10.865 ns; Loc. = LAB_X33_Y16; Fanout = 2; COMB Node = 'ram_addr_buf[12]~3410'
    Info: 9: + IC(0.187 ns) + CELL(0.624 ns) = 11.676 ns; Loc. = LAB_X33_Y16; Fanout = 2; COMB Node = 'Equal412~595'
    Info: 10: + IC(0.903 ns) + CELL(0.589 ns) = 13.168 ns; Loc. = LAB_X34_Y17; Fanout = 2; COMB Node = 'Equal412~606'
    Info: 11: + IC(1.270 ns) + CELL(0.614 ns) = 15.052 ns; Loc. = LAB_X32_Y13; Fanout = 1; COMB Node = 'Equal412~634'
    Info: 12: + IC(0.160 ns) + CELL(0.535 ns) = 15.747 ns; Loc. = LAB_X32_Y13; Fanout = 13; COMB Node = 'WideOr47~15176'
    Info: 13: + IC(1.484 ns) + CELL(0.855 ns) = 18.086 ns; Loc. = LAB_X36_Y16; Fanout = 1; REG Node = 'ram_addr_buf[7]'
    Info: Total cell delay = 5.959 ns ( 32.95 % )
    Info: Total interconnect delay = 12.127 ns ( 67.05 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 6% of the available device resources. Peak interconnect usage is 16%
    Info: The peak interconnect region extends from location X25_Y14 to location X37_Y27
Info: Fitter routing operations ending: elapsed time is 00:00:08
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Warning: Found 47 output pins without output pin load capacitance assignment
    Info: Pin "clk_1m_out" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "led0" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "led1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "led2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "led3" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "led4" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "led5" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "led6" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "led7" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "csn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "state_num_out[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "state_num_out[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "state_num_out[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "state_num_out[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "state_num_out[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "state_num_out[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "state_num_out[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "state_num_out[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "fifo_frame_num_out[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "fifo_frame_num_out[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "fifo_frame_num_out[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "fifo_frame_num_out[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "fifo_frame_num_out[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "fifo_frame_num_out[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "fifo_frame_num_out[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "fifo_frame_num_out[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ram_addr[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ram_addr[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ram_addr[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ram_addr[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ram_addr[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ram_addr[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ram_addr[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ram_addr[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ram_addr[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ram_addr[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ram_addr[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ram_addr[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ram_addr[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "sclk" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "clk_5m_out" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "veg_en" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "reset_out" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "test1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "test2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "send_finished" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "si" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Warning: Following 4 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
    Info: Pin state_num_out[5] has GND driving its datain port
    Info: Pin state_num_out[6] has GND driving its datain port
    Info: Pin state_num_out[7] has GND driving its datain port
    Info: Pin veg_en has VCC driving its datain port
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 4 warnings
    Info: Allocated 206 megabytes of memory during processing
    Info: Processing ended: Fri Aug 29 23:39:04 2008
    Info: Elapsed time: 00:00:38