cc2420interface.vhd

对cc2420无线模块的接口。接受到的数据都使用双口ROM的方式与后台核心控制部分传送。

               end if;
          end if;
-------------------------------------------------
        when initial_st1 =>
          if reset='1' then 
             next_state<=initial_st1;
          else 
             next_state<=initial_st2;
          end if;

        when initial_st2 =>
          if reset='1' then 
             next_state<=initial_st1;
          else if command_strobe_num/=0 then 
             next_state<=command_st1;
               elsif command_strobe_num=0 then
                   next_state<=initial_st4;
               end if;
          end if;

        when initial_st3 =>
          if reset='1' then 
             next_state<=initial_st1;
          else 
             next_state<=initial_st2;           
          end if;

        when initial_st4 =>
          if reset='1' then 
             next_state<=initial_st1;
          else if register_num/=0 then 
             next_state<=register_st1;
               elsif register_num=0 then
                   next_state<=initial_st6;
               end if;
          end if;

         when initial_st5 =>
          if reset='1' then 
             next_state<=initial_st1;
          else 
             next_state<=initial_st4;       
          end if;

         when initial_st6 =>
          if reset='1' then 
             next_state<=initial_st1;
          else if register_num=0 and command_strobe_num=0 then 
               next_state<=fifo_r_st1;
               else
                   next_state<=initial_st2;
               end if;
          end if;
-----------------------------------------------------------
         when fifo_r_st1 =>
          if reset='1' then 
             next_state<=initial_st1;
          else if fifo_r_delay_count=0 then 
               next_state<=fifo_r_st2;
               else
                   next_state<=fifo_r_st1;
               end if;
          end if;

         when fifo_r_st2 =>
          if reset='1' then 
             next_state<=initial_st1;
          else if write_command='1' then 
               next_state<=command_st1;
               else if write_register='1' then 
                    next_state<=register_st1;
                    else if write_fifo='1' or fifo_frame_num>=x"01" then-----------------------------------
                         next_state<=fifo_w_st1;
                         else if fifop_buf='1' then
								 next_state<=fifo_r_st3;
                              else next_state<=fifo_r_st2;
                              end if;
                         end if;
                    end if;
               end if;
          end if;
          
         
         when fifo_r_st3 =>
          if reset='1' then 
             next_state<=initial_st1;
          else if write_command='1' then 
               next_state<=command_st1;
               else if write_register='1' then 
                    next_state<=register_st1;
                    else if write_fifo='1' then
                         next_state<=fifo_w_st1;
                         else if fifo_r_count1=0 then
                              next_state<=fifo_r_st4;
                              else next_state<=fifo_r_st3;
                              end if;
                         end if;
                    end if;
               end if;
          end if;

         when fifo_r_st4 =>
          if reset='1' then 
             next_state<=initial_st1;
          else if write_command='1' then 
               next_state<=command_st1;
               else if write_register='1' then 
                    next_state<=register_st1;
                    else if write_fifo='1' then
                         next_state<=fifo_w_st1;
                         else if read_fifo_finished='1' then
                                 next_state<=fifo_r_st5;
                              else next_state<=fifo_r_st4;
                              end if;
                         end if;
                    end if;
               end if;
          end if;
         when fifo_r_st5 =>
          if reset='1' then 
             next_state<=initial_st1;
          else if write_command='1' then 
               next_state<=command_st1;
               else if write_register='1' then 
                    next_state<=register_st1;
                    else if write_fifo='1' then
                         next_state<=fifo_w_st1;
                         else if send_to_buf_finished='1' then
                              next_state<=fifo_r_st2;
                              else next_state<=fifo_r_st5;
                              end if;
                         end if;
                    end if;
               end if;
          end if;
------------------------------------------------------------
   when others =>next_state<=fifo_r_st2; 
   end case;
end if;
end process state_jump;
-------------------------------------------------------------
--------------------------------------------------------------
-------------------------------------------------------------
state_behav:process(sclk_buf,sclk_not,clk_5m,mainclk)
   begin
if rising_edge(clk_5m) then
 CASE current_state is
      when command_st1=>
           state_num<=x"01";
           csn_buf<='1';
           command_buf<=main_buf(1023 downto 1016);
           si_buf<=main_buf(1023);
           command_w_flag<='1';
           command_w_set_flag<='1';
           command_end_delay_set_flag<='1';
           command_end_delay_flag<='1';
           

      when command_st2=>
           state_num<=x"02";
           command_end_delay_flag<='1';
           command_end_delay_set_flag<='1';
           command_w_set_flag<='0';
              if command_num<=7 and command_num>=0 then
                 si_buf<=command_buf(command_num);---------------------------------------
              end if; 
           if command_num>=8 then
              csn_buf<='1';              
           elsif command_num<=7 then
              csn_buf<='0';                
           end if;
           if command_num=0 then
               command_w_flag<='1';
           else command_w_flag<='0';
           end if;
           
      
      when command_st3=>--------------------------------------------------------------
           state_num<=x"03";
           command_end_delay_set_flag<='0';
           if command_end_delay_count=0 then 
              csn_buf<='1';
              command_end_delay_flag<='1';
             
              else 
              csn_buf<='0';
              command_end_delay_flag<='0';
           end if;

-------------------------------------
      when register_st1=>
           state_num<=x"04";
           csn_buf<='1';
           register_buf<=main_buf(1023 downto 1000);
           si_buf<=register_buf(23);
           register_w_flag<='1';
           register_w_set_flag<='1';
           register_end_delay_flag<='1';
           register_end_delay_set_flag<='1';

       when register_st2=>
           state_num<=x"05";
           register_w_set_flag<='0';
              if register_count<=23 and register_count>=0 then
                 si_buf<=register_buf(register_count);----------
              --else si_buf<='1';
              end if; 
           if register_count>=24 then
              csn_buf<='1';
                           
           elsif register_count<=23 and register_count>=0 then
                csn_buf<='0';                
           end if;
           if register_count>=1 then
              register_w_flag<='0';
           elsif register_count=0 then
              register_w_flag<='1';
           end if;

       when register_st3=>
           state_num<=x"06";
           register_end_delay_set_flag<='0';
           if register_end_delay_count=0 then -------------------
              csn_buf<='1';
              register_end_delay_flag<='1';
           else 
              csn_buf<='0';
              register_end_delay_flag<='0';
           end if;
-----------------------------------------------------------
       when fifo_w_st1 =>
           state_num<=x"07";
           fifo_w_delay_set<='0';
           csn_buf<='1';
           fifo_w_set_flag<='1';
           fifo_w_end_delay_set_flag<='1'; 
           fifo_w_jump_delay_set_flag<='1'; 
           fifo_w_buf(1015 downto 1008)<=x"3e";			  
           fifo_w_buf(1007 downto 984)<=x"0f00ff";---------5555555555555555555550000";
           fifo_w_buf(983 downto 976)<=fifo_frame_num;
           fifo_w_buf(975 downto 16)<=fifo_w_buf_in;
           fifo_w_buf(15 downto 0)<=x"0000";
           si_buf<=fifo_w_buf(135);
           if fifo_w_delay_count=0 then     -----------------
              fifo_w_delay_flag<='1';
           else fifo_w_delay_flag<='0';
           end if;
       if fifo_w_delay_count>=7000 then
                
          case fifo_frame_num is
               when x"29" => start_add<=x"0000";----0
                               end_add<=x"0077"; 
               when x"28" => start_add<=x"0078";----120
                               end_add<=x"00ef";------239
               when x"27" => start_add<=x"00f0";----240
                              end_add<=x"0167";----359 
              when x"26" => start_add<=x"0168";----360
                              end_add<=x"01df"; ---479
              when x"25" => start_add<=x"01e0";----480
                              end_add<=x"0257"; ---599
              when x"24" => start_add<=x"0258";----600
                              end_add<=x"02cf";----719
              when x"23" => start_add<=x"02d0";----720
                              end_add<=x"0347";----8
              when x"22" => start_add<=x"0348";----840
                              end_add<=x"03bf"; 
              when x"21" => start_add<=x"03c0";----960
                              end_add<=x"0437"; ---
              when x"20" => start_add<=x"0438";----1080
                              end_add<=x"045f";
              when x"1f" => start_add<=x"0460";----1200
                              end_add<=x"0527"; 
              when x"1e" => start_add<=x"0528";----1320
                              end_add<=x"059f"; 
              when x"1d" => start_add<=x"05a0";----1440
                              end_add<=x"0617"; 
              when x"1c" => start_add<=x"0618";----1560
                              end_add<=x"068f";
              when x"1b" => start_add<=x"0690";----1680
                              end_add<=x"0707"; 
              when x"1a" => start_add<=x"0708";----1800
                              end_add<=x"077f"; 
              when x"19" => start_add<=x"0780";----1920
                              end_add<=x"07f7"; 
              when x"18" => start_add<=x"07f8";----2040
                              end_add<=x"086f";
              when x"17" => start_add<=x"0870";----2160
                              end_add<=x"08e7"; 
              when x"16" => start_add<=x"08e8";----2280
                              end_add<=x"095f"; 
              when x"15" => start_add<=x"0960";----2400
                              end_add<=x"09d7"; 
              when x"14" => start_add<=x"09d8";----2520
                              end_add<=x"0a4f";
              when x"13" => start_add<=x"0a50";----2640
                              end_add<=x"0ac7"; 
              when x"12" => start_add<=x"0ac8";----2760
                              end_add<=x"0b3f"; 
              when x"11" => start_add<=x"0b40";----2880
                              end_add<=x"0bb7"; 
              when x"10" => start_add<=x"0bb8";----3000
                              end_add<=x"0c2f";
              when x"0f" => start_add<=x"0c30";----3120
                              end_add<=x"0ca7"; 
              when x"0e" => start_add<=x"0ca8";----3240
                              end_add<=x"0d1f"; 
              when x"0d" => start_add<=x"0d20";----3360