cc2420interface.vhd

对cc2420无线模块的接口。接受到的数据都使用双口ROM的方式与后台核心控制部分传送。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

ENTITY cc2420interface IS
	
	PORT
	(
		newreset          		: IN	STD_LOGIC;
		fifo         		: IN	STD_LOGIC;
		mainclk        		: IN	STD_LOGIC;
		clk_1m_out        		: out	STD_LOGIC;
		fifop         		: IN	STD_LOGIC;
		cca         		: IN	STD_LOGIC;
		sfd         		: IN	STD_LOGIC;
---------------------------------------------------LED
		led0           : out std_logic;
		led1           : out std_logic;
		led2           : out std_logic;
		led3           : out std_logic;
		led4           : out std_logic;
		led5           : out std_logic;
		led6           : out std_logic;
		led7           : out std_logic;
------------------------------------------------------
		so          		: IN	STD_LOGIC;
		csn             	: OUT	STD_LOGIC;
		state_num_out      	: OUT	STD_LOGIC_vector(7 downto 0);-------test----------
		fifo_frame_num_out  : out   std_logic_vector(7 downto 0);-----------test--
		ram_addr            : out   std_logic_vector(12 downto 0);--------to ram
		ram_data            : in    std_logic_vector(7 downto 0);---------to ram
		sclk              	: OUT	STD_LOGIC; --125khz
		clk_5m_out        	: OUT	STD_LOGIC; --5mhz---------------------to ram
		veg_en              : out   std_logic;------
		reset_out     		: out	STD_LOGIC;
		test1            	: OUT	STD_LOGIC;----------test----------
		test2            	: OUT	STD_LOGIC;--------------test------
		write_fifo_in       : in    std_logic;
		send_finished       : out   std_logic;
		------------j-
		si              	: OUT	STD_LOGIC
		
	);
END cc2420interface;
ARCHITECTURE state_behav OF cc2420interface IS
    TYPE states IS (command_st1, command_st2, command_st3,initial_st1,initial_st2,initial_st3,initial_st4,
                    initial_st5,initial_st6,register_st1,register_st2,register_st3,
                    fifo_w_st1,fifo_w_st2,fifo_w_st3,fifo_w_st4,
                    fifo_r_st1,fifo_r_st2,fifo_r_st3,fifo_r_st4,fifo_r_st5);
	SIGNAL current_state  : states;
	SIGNAL next_state     : states;
	--constant send_delay   
	signal clk_count1              : integer range 0 to 199;-----------125kHz-
	signal clk_count2              : integer range 0 to 50;-----------
	signal clk_count_5m            : integer range 0 to 4;
	signal clk_count_1m            : integer range 0 to 24;
	--signal command_in_count        : integer range 0 to 8;-----------------
	signal command_num             : integer range 0 to 8;--------------------------
	signal command_end_delay_count : integer range 0 to 64;----------------------------
	signal register_end_delay_count: integer range 0 to 64;----------------------------
	signal register_count          : integer range 0 to 24;-----------------------------------
	signal fifo_w_delay_count      : integer range 0 to 100000;-------------------------
	signal fifo_w_jump_delay_count : integer range 0 to 1023;----------------------------------
	signal fifo_w_end_delay_count  : integer range 0 to 40;---------------------------------
	signal fifo_w_count            : integer range 0 to 1016;-------------------------------------
	signal fifo_r_delay_count      : integer range 0 to 1023;--------------------------------------
	signal fifo_r_count            : integer range 0 to 1024;--------------------------------------
	--signal fifo_r_end_delay_count      : integer range 0 to 1023;------------------------------
	signal fifo_r_count1           : integer range 0 to 9;--------------------------------------
	signal command_strobe_num      : integer range 0 to 4;---------------------------------------
	signal register_num            : integer range 0 to 10;-------------------------------------
	signal  send_start_count       : integer range 0 to 1023;----------------------------------
	signal fifo_send_num           : integer range 0 to 41;
	signal byte_count              : integer range 0 to 1015;
	signal fifo_w_send_count       : integer range 0 to 7;
	signal state_num      : std_logic_vector(7 downto 0);------------------------------------
	signal fifo_frame_num : std_logic_vector(7 downto 0):=x"00";
	signal fifo_w_buf_in  : std_logic_vector(959 downto 0);
	signal command_buf    : std_logic_vector(7 downto 0);
	signal register_buf   : std_logic_vector(23 downto 0);
	signal fifo_w_buf     : std_logic_vector(1015 downto 0);
	signal fifo_r_buf     : std_logic_vector(123 downto 0);
	signal fifo_r_buf1    : std_logic_vector(7 downto 0);
	signal main_buf       : std_logic_vector(1023 downto 0);
	signal ram_addr_buf   : std_logic_vector(12 downto 0);
	signal start_add      : std_logic_vector(15 downto 0);
	signal start_add_buf  : std_logic_vector(12 downto 0);
	signal end_add        : std_logic_vector(15 downto 0);
	signal ram_data_buf   : std_logic_vector(7 downto 0);
	signal command_end_delay_flag       : std_logic;
	signal command_end_delay_set_flag   : std_logic;
	signal command_w_flag               : std_logic;
	signal command_w_set_flag           : std_logic;
	signal register_end_delay_flag       : std_logic;
	signal register_end_delay_set_flag   : std_logic;
	signal register_w_flag               : std_logic;
	signal register_w_set_flag           : std_logic;
	signal fifo_w_end_delay_flag        : std_logic;
	signal fifo_w_end_delay_set_flag    : std_logic;
	signal fifo_w_flag                  : std_logic;
	signal fifo_w_set_flag              : std_logic;
	signal fifo_w_delay_flag            : std_logic;
	signal fifo_w_delay_set             : std_logic;
	signal fifo_w_jump_delay_flag       : std_logic;
	signal fifo_w_jump_delay_set_flag   : std_logic;
	signal fifo_r_flag                  : std_logic;
	signal fifo_r_set_flag              : std_logic;
	signal fifo_r_flag1                 : std_logic;
	signal fifo_r_set_flag1             : std_logic;
	signal fifo_r_delay_flag            : std_logic;
	signal fifo_r_delay_set_flag        : std_logic;
	signal sclk_buf       : std_logic;
	signal clk_5m_buf     : std_logic;
	signal csn_buf        : std_logic;
	signal si_buf         : std_logic;
	signal so_buf         : std_logic;
	signal fifo_buf       : std_logic;
	signal fifop_buf      : std_logic;
	signal sfd_buf        : std_logic;
	signal cca_buf        : std_logic;
	signal clk_5m         : std_logic;
	signal clk_1m         : std_logic;
	signal write_fifo     : std_logic;
	signal write_register : std_logic;
	signal write_command  : std_logic;
	signal send_start_temp1 :std_logic;
	signal send_start_temp2 :std_logic;
	signal send_start_temp3 :std_logic;
	signal read_fifo_finished       : std_logic;
	signal send_to_buf_finished       : std_logic;
	SIGNAL sclk_not       : STD_LOGIC;
	SIGNAL initial_active : STD_LOGIC;
	SIGNAL first_byte     : STD_LOGIC_vector(7 downto 0);
-----------------------------------------------
	signal reset :std_logic;
	signal clk500k_buf :std_logic;
BEGIN
---------------------------------------------------------

---------------------------------------------------------
	process(mainclk)
	variable cnt : integer range 0 to 100;
	begin
		if newreset='1' then
			reset<='1';
			reset_out<='0';
			cnt:=0;
		elsif rising_edge(mainclk) then
			if cnt>=100 then
				reset<=newreset;
			else cnt:=cnt+1;
			end if;
			reset_out<=not newreset;
		end if;
	end process;
-------------------------------------------------------------------------------
---------------------------------------------------
-------------------------------------------------------------------------------
	clk500k_creat:	process (mainclk,clk_count1)
    begin 
	   if reset='1' then
			clk_count2<=0;
			clk500k_buf<='0';
		else if rising_edge(mainclk) then
				if clk_count2>=24 then
					clk_count2<=0;
					clk500k_buf<=not clk500k_buf;
				elsif clk_count2<24 then
              clk_count2<=clk_count2+1;
				end if;
			  end if;
      end if;
end process clk500k_creat;

-------------------------------------------------------------------------------
-----------------------------------------------
-------------------------------------------------------------------------------
sclk_creat:	process (mainclk,clk_count1)
    begin 
  if reset='1' then 
     clk_count1<=0;
     sclk_buf<='0';
  else if rising_edge(mainclk) then
        if clk_count1>=199 then
           clk_count1<=0;
           sclk_buf<=not sclk_buf;
        elsif clk_count1<199 then
              clk_count1<=clk_count1+1;
        end if;
       end if;
   end if;
end process sclk_creat;

clk_5m_creat:process(mainclk,clk_count_5m)
    begin
   if rising_edge(mainclk) then
      if clk_count_5m>=4 then 
         clk_count_5m<=0;
         clk_5m<=not clk_5m;
      else clk_count_5m<= clk_count_5m+1;
      end if;
   end if;

end process clk_5m_creat;

clk_1m_creat:process(mainclk,clk_count_1m)
    begin
   if rising_edge(mainclk) then
      if clk_count_1m>=24 then 
         clk_count_1m<=0;
         clk_1m<=not clk_1m;
      else clk_count_1m<= clk_count_1m+1;
      end if;
   end if;

end process clk_1m_creat;
-----------------------------------------------------------
-----------------------------------------------------------
state_jump:process(current_state,mainclk,clk_5m)
   begin 
if rising_edge(mainclk) then
   case current_state is
      when command_st1 => 
          if reset='1' then 
             next_state<=initial_st1;
          else 
             next_state<=command_st2;
               
              
          end if;
       when command_st2 =>
          if reset='1' then 
             next_state<=initial_st1;
          else if command_num=0 then
               next_state<=command_st3;
               else next_state<=command_st2;
               end if;
          end if;
       when command_st3 =>
         if reset='1' then 
            next_state<=initial_st1;
         else if command_end_delay_count=0 then
                 if initial_active='1' then
                 next_state<=initial_st3;
                 elsif initial_active='0' then
                 next_state<=fifo_r_st2;
               else next_state<=command_st3;
                 end if;
               end if;
         end if;
-----------------------------------------------------
       when register_st1 =>
         if reset='1' then 
             next_state<=initial_st1;
         else next_state<=register_st2;      
         end if;
       when register_st2 =>
          if reset='1' then 
             next_state<=initial_st1;
          else if register_count=0 then 
             next_state<=register_st3;
               else next_state<=register_st2;
               end if;
          end if;
       when register_st3 =>
          if reset='1' then 
             next_state<=initial_st1;
          else if register_end_delay_count=0 then
                  if initial_active='1' then 
                     next_state<=initial_st5;
                  elsif initial_active='0' then
                        next_state<=fifo_r_st2;
                  end if;
               end if;
          end if;
-------------------------------------------------------
       when fifo_w_st1 =>
          if reset='1' then 
             next_state<=initial_st1;
          else if fifo_w_delay_count=0 then 
             next_state<=fifo_w_st2;
               else  next_state<=fifo_w_st1;
               end if;
          end if;
        when fifo_w_st2 =>
          if reset='1' then 
             next_state<=initial_st1;
          else if fifo_w_count=0 then 
                  next_state<=fifo_w_st3;
               else  next_state<=fifo_w_st2;
               end if;
          end if;
        when fifo_w_st3 =>
          if reset='1' then 
             next_state<=initial_st1;
          else if fifo_w_end_delay_count=0 then 
             next_state<=fifo_w_st4;
               else  next_state<=fifo_w_st3;
               end if;
          end if;
        when fifo_w_st4 =>
          if reset='1' then 
             next_state<=initial_st1;
          else if fifo_w_jump_delay_count=0 then
             next_state<=command_st1;-------------------------------------
               else next_state<=fifo_w_st4;