cc2420interface.map.qmsg

对cc2420无线模块的接口。接受到的数据都使用双口ROM的方式与后台核心控制部分传送。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Aug 29 23:36:35 2008 " "Info: Processing started: Fri Aug 29 23:36:35 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off cc2420interface -c cc2420interface " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cc2420interface -c cc2420interface" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cc2420interface.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file cc2420interface.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cc2420interface-state_behav " "Info: Found design unit 1: cc2420interface-state_behav" {  } { { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 46 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 cc2420interface " "Info: Found entity 1: cc2420interface" {  } { { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "cc2420interface " "Info: Elaborating entity \"cc2420interface\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_L2_VRFC_OBJECT_ASSIGNED_NOT_READ" "fifo_r_buf cc2420interface.vhd(83) " "Warning (10036): Verilog HDL or VHDL warning at cc2420interface.vhd(83): object \"fifo_r_buf\" assigned a value but never read" {  } { { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 83 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_L2_VRFC_OBJECT_ASSIGNED_NOT_READ" "end_add cc2420interface.vhd(89) " "Warning (10036): Verilog HDL or VHDL warning at cc2420interface.vhd(89): object \"end_add\" assigned a value but never read" {  } { { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 89 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "write_register cc2420interface.vhd(125) " "Warning (10541): VHDL Signal Declaration warning at cc2420interface.vhd(125): used implicit default value for signal \"write_register\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." {  } { { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 125 0 0 } }  } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0}
{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "write_command cc2420interface.vhd(126) " "Warning (10541): VHDL Signal Declaration warning at cc2420interface.vhd(126): used implicit default value for signal \"write_command\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." {  } { { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 126 0 0 } }  } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "newreset cc2420interface.vhd(145) " "Warning (10492): VHDL Process Statement warning at cc2420interface.vhd(145): signal \"newreset\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 145 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "reset cc2420interface.vhd(162) " "Warning (10492): VHDL Process Statement warning at cc2420interface.vhd(162): signal \"reset\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 162 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "reset cc2420interface.vhd(181) " "Warning (10492): VHDL Process Statement warning at cc2420interface.vhd(181): signal \"reset\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 181 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "fifo_w_delay_count cc2420interface.vhd(1671) " "Warning (10492): VHDL Process Statement warning at cc2420interface.vhd(1671): signal \"fifo_w_delay_count\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 1671 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "fifo_w_delay_count cc2420interface.vhd(1673) " "Warning (10492): VHDL Process Statement warning at cc2420interface.vhd(1673): signal \"fifo_w_delay_count\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 1673 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "fifo_w_delay_count cc2420interface.vhd(1767) " "Warning (10492): VHDL Process Statement warning at cc2420interface.vhd(1767): signal \"fifo_w_delay_count\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 1767 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "write_fifo cc2420interface.vhd(1771) " "Warning (10492): VHDL Process Statement warning at cc2420interface.vhd(1771): signal \"write_fifo\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 1771 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "fifo_w_delay_count cc2420interface.vhd(1774) " "Warning (10492): VHDL Process Statement warning at cc2420interface.vhd(1774): signal \"fifo_w_delay_count\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 1774 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "send_to_buf_finished High " "Info: Power-up level of register \"send_to_buf_finished\" is not specified -- using power-up level of High to minimize register" {  } { { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 131 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "send_to_buf_finished data_in VCC " "Warning: Reduced register \"send_to_buf_finished\" with stuck data_in port to stuck value VCC" {  } { { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 131 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "fifo_r_buf1\[0\] High " "Info: Power-up level of register \"fifo_r_buf1\[0\]\" is not specified -- using power-up level of High to minimize register" {  } { { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 453 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "fifo_r_buf1\[0\] data_in VCC " "Warning: Reduced register \"fifo_r_buf1\[0\]\" with stuck data_in port to stuck value VCC" {  } { { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 453 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "fifo_r_buf1\[1\] High " "Info: Power-up level of register \"fifo_r_buf1\[1\]\" is not specified -- using power-up level of High to minimize register" {  } { { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 453 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "fifo_r_buf1\[1\] data_in VCC " "Warning: Reduced register \"fifo_r_buf1\[1\]\" with stuck data_in port to stuck value VCC" {  } { { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 453 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "fifo_r_buf1\[2\] High " "Info: Power-up level of register \"fifo_r_buf1\[2\]\" is not specified -- using power-up level of High to minimize register" {  } { { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 453 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}