cc2420interface.sim.qmsg

对cc2420无线模块的接口。接受到的数据都使用双口ROM的方式与后台核心控制部分传送。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 30 00:51:55 2008 " "Info: Processing started: Sat Aug 30 00:51:55 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --read_settings_files=on --write_settings_files=off cc2420interface -c cc2420interface " "Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off cc2420interface -c cc2420interface" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISDB_SOURCE_VECTOR_FILE_USED" "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vwf " "Info: Using vector source file \"D:/我的文档/vhdl design/cc2420interface/cc2420interface.vwf\"" {  } {  } 0 0 "Using vector source file \"%1!s!\"" 0 0}
{ "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_FOUND" "" "Info: Inverted registers were found during simulation" { { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|command_end_delay_count\[5\] " "Info: Register: \|cc2420interface\|command_end_delay_count\[5\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|command_end_delay_count\[3\] " "Info: Register: \|cc2420interface\|command_end_delay_count\[3\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|register_end_delay_count\[5\] " "Info: Register: \|cc2420interface\|register_end_delay_count\[5\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|register_end_delay_count\[3\] " "Info: Register: \|cc2420interface\|register_end_delay_count\[3\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|fifo_w_end_delay_count\[5\] " "Info: Register: \|cc2420interface\|fifo_w_end_delay_count\[5\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|fifo_w_end_delay_count\[3\] " "Info: Register: \|cc2420interface\|fifo_w_end_delay_count\[3\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|register_count\[4\] " "Info: Register: \|cc2420interface\|register_count\[4\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|register_count\[3\] " "Info: Register: \|cc2420interface\|register_count\[3\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|fifo_r_count\[6\] " "Info: Register: \|cc2420interface\|fifo_r_count\[6\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|fifo_r_count\[5\] " "Info: Register: \|cc2420interface\|fifo_r_count\[5\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|fifo_r_count\[4\] " "Info: Register: \|cc2420interface\|fifo_r_count\[4\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|fifo_r_count\[3\] " "Info: Register: \|cc2420interface\|fifo_r_count\[3\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|fifo_r_count\[1\] " "Info: Register: \|cc2420interface\|fifo_r_count\[1\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|fifo_r_count\[0\] " "Info: Register: \|cc2420interface\|fifo_r_count\[0\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|reset " "Info: Register: \|cc2420interface\|reset" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|fifo_w_count\[9\] " "Info: Register: \|cc2420interface\|fifo_w_count\[9\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|fifo_w_count\[8\] " "Info: Register: \|cc2420interface\|fifo_w_count\[8\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|fifo_w_count\[7\] " "Info: Register: \|cc2420interface\|fifo_w_count\[7\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|fifo_w_count\[6\] " "Info: Register: \|cc2420interface\|fifo_w_count\[6\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|fifo_w_count\[5\] " "Info: Register: \|cc2420interface\|fifo_w_count\[5\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|fifo_w_count\[4\] " "Info: Register: \|cc2420interface\|fifo_w_count\[4\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|fifo_w_count\[3\] " "Info: Register: \|cc2420interface\|fifo_w_count\[3\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|fifo_r_count1\[0\] " "Info: Register: \|cc2420interface\|fifo_r_count1\[0\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|fifo_r_count1\[3\] " "Info: Register: \|cc2420interface\|fifo_r_count1\[3\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|command_num\[3\] " "Info: Register: \|cc2420interface\|command_num\[3\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|fifo_w_delay_count\[11\] " "Info: Register: \|cc2420interface\|fifo_w_delay_count\[11\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|fifo_w_delay_count\[10\] " "Info: Register: \|cc2420interface\|fifo_w_delay_count\[10\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|fifo_w_delay_count\[12\] " "Info: Register: \|cc2420interface\|fifo_w_delay_count\[12\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|fifo_w_delay_count\[9\] " "Info: Register: \|cc2420interface\|fifo_w_delay_count\[9\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|fifo_w_delay_count\[8\] " "Info: Register: \|cc2420interface\|fifo_w_delay_count\[8\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|fifo_w_delay_count\[6\] " "Info: Register: \|cc2420interface\|fifo_w_delay_count\[6\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|fifo_w_jump_delay_count\[9\] " "Info: Register: \|cc2420interface\|fifo_w_jump_delay_count\[9\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|fifo_w_jump_delay_count\[8\] " "Info: Register: \|cc2420interface\|fifo_w_jump_delay_count\[8\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|fifo_w_jump_delay_count\[7\] " "Info: Register: \|cc2420interface\|fifo_w_jump_delay_count\[7\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|fifo_w_jump_delay_count\[6\] " "Info: Register: \|cc2420interface\|fifo_w_jump_delay_count\[6\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|fifo_w_jump_delay_count\[5\] " "Info: Register: \|cc2420interface\|fifo_w_jump_delay_count\[5\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|fifo_w_jump_delay_count\[3\] " "Info: Register: \|cc2420interface\|fifo_w_jump_delay_count\[3\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|fifo_r_delay_count\[9\] " "Info: Register: \|cc2420interface\|fifo_r_delay_count\[9\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|fifo_r_delay_count\[8\] " "Info: Register: \|cc2420interface\|fifo_r_delay_count\[8\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|fifo_r_delay_count\[7\] " "Info: Register: \|cc2420interface\|fifo_r_delay_count\[7\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|fifo_r_delay_count\[6\] " "Info: Register: \|cc2420interface\|fifo_r_delay_count\[6\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|fifo_r_delay_count\[5\] " "Info: Register: \|cc2420interface\|fifo_r_delay_count\[5\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|cc2420interface\|fifo_r_delay_count\[3\] " "Info: Register: \|cc2420interface\|fifo_r_delay_count\[3\]" {  } {  } 0 0 "Register: %1!s!" 0 0}  } {  } 0 0 "Inverted registers were found during simulation" 0 0}
{ "Info" "IEDS_MAX_TRANSITION_COUNT" "" "Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled" { { "Info" "IEDS_MAX_TRANSITION_COUNT_EXP" "" "Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." {  } {  } 0 0 "Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." 0 0}  } {  } 0 0 "Option to preserve fewer signal transitions to reduce memory requirements is enabled" 0 0}
{ "Info" "IEDS_SUB_SIMULATION_COUNT" "1 " "Info: Simulation partitioned into 1 sub-simulations" {  } {  } 0 0 "Simulation partitioned into %1!d! sub-simulations" 0 0}
{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" "     44.89 % " "Info: Simulation coverage is      44.89 %" {  } {  } 0 0 "Simulation coverage is %1!s!" 0 0}
{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "11294059 " "Info: Number of transitions in simulation is 11294059" {  } {  } 0 0 "Number of transitions in simulation is %1!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Simulator 0 s 0 s Quartus II " "Info: Quartus II Simulator was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "117 " "Info: Allocated 117 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 30 01:16:03 2008 " "Info: Processing ended: Sat Aug 30 01:16:03 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:24:08 " "Info: Elapsed time: 00:24:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}