cc2420interface.tan.qmsg

对cc2420无线模块的接口。接受到的数据都使用双口ROM的方式与后台核心控制部分传送。

{ "Info" "ITDB_TSU_RESULT" "next_state.fifo_r_st2 fifop mainclk 7.684 ns register " "Info: tsu for register \"next_state.fifo_r_st2\" (data pin = \"fifop\", clock pin = \"mainclk\") is 7.684 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.817 ns + Longest pin register " "Info: + Longest pin to register delay is 10.817 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns fifop 1 PIN PIN_B9 3 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_B9; Fanout = 3; PIN Node = 'fifop'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { fifop } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.328 ns) + CELL(0.624 ns) 7.886 ns Selector17~670 2 COMB LCCOMB_X15_Y13_N20 1 " "Info: 2: + IC(6.328 ns) + CELL(0.624 ns) = 7.886 ns; Loc. = LCCOMB_X15_Y13_N20; Fanout = 1; COMB Node = 'Selector17~670'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.952 ns" { fifop Selector17~670 } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 223 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.059 ns) + CELL(0.319 ns) 9.264 ns Selector17~671 3 COMB LCCOMB_X16_Y13_N24 1 " "Info: 3: + IC(1.059 ns) + CELL(0.319 ns) = 9.264 ns; Loc. = LCCOMB_X16_Y13_N24; Fanout = 1; COMB Node = 'Selector17~671'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.378 ns" { Selector17~670 Selector17~671 } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 223 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.079 ns) + CELL(0.366 ns) 10.709 ns Selector17~672 4 COMB LCCOMB_X15_Y14_N26 1 " "Info: 4: + IC(1.079 ns) + CELL(0.366 ns) = 10.709 ns; Loc. = LCCOMB_X15_Y14_N26; Fanout = 1; COMB Node = 'Selector17~672'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.445 ns" { Selector17~671 Selector17~672 } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 223 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 10.817 ns next_state.fifo_r_st2 5 REG LCFF_X15_Y14_N27 3 " "Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 10.817 ns; Loc. = LCFF_X15_Y14_N27; Fanout = 3; REG Node = 'next_state.fifo_r_st2'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { Selector17~672 next_state.fifo_r_st2 } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.351 ns ( 21.73 % ) " "Info: Total cell delay = 2.351 ns ( 21.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.466 ns ( 78.27 % ) " "Info: Total interconnect delay = 8.466 ns ( 78.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.817 ns" { fifop Selector17~670 Selector17~671 Selector17~672 next_state.fifo_r_st2 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "10.817 ns" { fifop fifop~combout Selector17~670 Selector17~671 Selector17~672 next_state.fifo_r_st2 } { 0.000ns 0.000ns 6.328ns 1.059ns 1.079ns 0.000ns } { 0.000ns 0.934ns 0.624ns 0.319ns 0.366ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 52 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mainclk destination 3.093 ns - Shortest register " "Info: - Shortest clock path from clock \"mainclk\" to destination register is 3.093 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns mainclk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'mainclk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { mainclk } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.000 ns) 1.357 ns mainclk~clkctrl 2 COMB CLKCTRL_G3 1047 " "Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.357 ns; Loc. = CLKCTRL_G3; Fanout = 1047; COMB Node = 'mainclk~clkctrl'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.257 ns" { mainclk mainclk~clkctrl } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.070 ns) + CELL(0.666 ns) 3.093 ns next_state.fifo_r_st2 3 REG LCFF_X15_Y14_N27 3 " "Info: 3: + IC(1.070 ns) + CELL(0.666 ns) = 3.093 ns; Loc. = LCFF_X15_Y14_N27; Fanout = 3; REG Node = 'next_state.fifo_r_st2'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.736 ns" { mainclk~clkctrl next_state.fifo_r_st2 } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.766 ns ( 57.10 % ) " "Info: Total cell delay = 1.766 ns ( 57.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.327 ns ( 42.90 % ) " "Info: Total interconnect delay = 1.327 ns ( 42.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.093 ns" { mainclk mainclk~clkctrl next_state.fifo_r_st2 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.093 ns" { mainclk mainclk~combout mainclk~clkctrl next_state.fifo_r_st2 } { 0.000ns 0.000ns 0.257ns 1.070ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.817 ns" { fifop Selector17~670 Selector17~671 Selector17~672 next_state.fifo_r_st2 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "10.817 ns" { fifop fifop~combout Selector17~670 Selector17~671 Selector17~672 next_state.fifo_r_st2 } { 0.000ns 0.000ns 6.328ns 1.059ns 1.079ns 0.000ns } { 0.000ns 0.934ns 0.624ns 0.319ns 0.366ns 0.108ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.093 ns" { mainclk mainclk~clkctrl next_state.fifo_r_st2 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.093 ns" { mainclk mainclk~combout mainclk~clkctrl next_state.fifo_r_st2 } { 0.000ns 0.000ns 0.257ns 1.070ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "mainclk sclk csn_buf 15.524 ns register " "Info: tco from clock \"mainclk\" to destination pin \"sclk\" through register \"csn_buf\" is 15.524 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mainclk source 6.148 ns + Longest register " "Info: + Longest clock path from clock \"mainclk\" to source register is 6.148 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns mainclk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'mainclk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { mainclk } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.000 ns) 1.357 ns mainclk~clkctrl 2 COMB CLKCTRL_G3 1047 " "Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.357 ns; Loc. = CLKCTRL_G3; Fanout = 1047; COMB Node = 'mainclk~clkctrl'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.257 ns" { mainclk mainclk~clkctrl } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.079 ns) + CELL(0.970 ns) 3.406 ns clk_5m 3 REG LCFF_X24_Y26_N1 3 " "Info: 3: + IC(1.079 ns) + CELL(0.970 ns) = 3.406 ns; Loc. = LCFF_X24_Y26_N1; Fanout = 3; REG Node = 'clk_5m'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.049 ns" { mainclk~clkctrl clk_5m } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 197 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.005 ns) + CELL(0.000 ns) 4.411 ns clk_5m~clkctrl 4 COMB CLKCTRL_G8 1138 " "Info: 4: + IC(1.005 ns) + CELL(0.000 ns) = 4.411 ns; Loc. = CLKCTRL_G8; Fanout = 1138; COMB Node = 'clk_5m~clkctrl'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.005 ns" { clk_5m clk_5m~clkctrl } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 197 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.071 ns) + CELL(0.666 ns) 6.148 ns csn_buf 5 REG LCFF_X14_Y14_N19 5 " "Info: 5: + IC(1.071 ns) + CELL(0.666 ns) = 6.148 ns; Loc. = LCFF_X14_Y14_N19; Fanout = 5; REG Node = 'csn_buf'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.737 ns" { clk_5m~clkctrl csn_buf } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 453 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.736 ns ( 44.50 % ) " "Info: Total cell delay = 2.736 ns ( 44.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.412 ns ( 55.50 % ) " "Info: Total interconnect delay = 3.412 ns ( 55.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.148 ns" { mainclk mainclk~clkctrl clk_5m clk_5m~clkctrl csn_buf } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.148 ns" { mainclk mainclk~combout mainclk~clkctrl clk_5m clk_5m~clkctrl csn_buf } { 0.000ns 0.000ns 0.257ns 1.079ns 1.005ns 1.071ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 453 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.072 ns + Longest register pin " "Info: + Longest register to pin delay is 9.072 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns csn_buf 1 REG LCFF_X14_Y14_N19 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y14_N19; Fanout = 5; REG Node = 'csn_buf'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { csn_buf } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 453 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.481 ns) + CELL(0.202 ns) 3.683 ns sclk~9 2 COMB LCCOMB_X49_Y14_N20 1 " "Info: 2: + IC(3.481 ns) + CELL(0.202 ns) = 3.683 ns; Loc. = LCCOMB_X49_Y14_N20; Fanout = 1; COMB Node = 'sclk~9'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.683 ns" { csn_buf sclk~9 } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.153 ns) + CELL(3.236 ns) 9.072 ns sclk 3 PIN PIN_AB20 0 " "Info: 3: + IC(2.153 ns) + CELL(3.236 ns) = 9.072 ns; Loc. = PIN_AB20; Fanout = 0; PIN Node = 'sclk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.389 ns" { sclk~9 sclk } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.438 ns ( 37.90 % ) " "Info: Total cell delay = 3.438 ns ( 37.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.634 ns ( 62.10 % ) " "Info: Total interconnect delay = 5.634 ns ( 62.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/q