cc2420interface.tan.qmsg

对cc2420无线模块的接口。接受到的数据都使用双口ROM的方式与后台核心控制部分传送。

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "write_fifo_in register register write_fifo write_fifo 360.1 MHz Internal " "Info: Clock \"write_fifo_in\" Internal fmax is restricted to 360.1 MHz between source register \"write_fifo\" and destination register \"write_fifo\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.777 ns " "Info: fmax restricted to clock pin edge rate 2.777 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.316 ns + Longest register register " "Info: + Longest register to register delay is 1.316 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns write_fifo 1 REG LCFF_X32_Y18_N23 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X32_Y18_N23; Fanout = 9; REG Node = 'write_fifo'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { write_fifo } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 1768 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.437 ns) + CELL(0.206 ns) 0.643 ns write_fifo~36 2 COMB LCCOMB_X32_Y18_N18 1 " "Info: 2: + IC(0.437 ns) + CELL(0.206 ns) = 0.643 ns; Loc. = LCCOMB_X32_Y18_N18; Fanout = 1; COMB Node = 'write_fifo~36'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.643 ns" { write_fifo write_fifo~36 } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 1768 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.359 ns) + CELL(0.206 ns) 1.208 ns write_fifo~37 3 COMB LCCOMB_X32_Y18_N22 1 " "Info: 3: + IC(0.359 ns) + CELL(0.206 ns) = 1.208 ns; Loc. = LCCOMB_X32_Y18_N22; Fanout = 1; COMB Node = 'write_fifo~37'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.565 ns" { write_fifo~36 write_fifo~37 } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 1768 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 1.316 ns write_fifo 4 REG LCFF_X32_Y18_N23 9 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 1.316 ns; Loc. = LCFF_X32_Y18_N23; Fanout = 9; REG Node = 'write_fifo'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { write_fifo~37 write_fifo } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 1768 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.520 ns ( 39.51 % ) " "Info: Total cell delay = 0.520 ns ( 39.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.796 ns ( 60.49 % ) " "Info: Total interconnect delay = 0.796 ns ( 60.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.316 ns" { write_fifo write_fifo~36 write_fifo~37 write_fifo } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "1.316 ns" { write_fifo write_fifo~36 write_fifo~37 write_fifo } { 0.000ns 0.437ns 0.359ns 0.000ns } { 0.000ns 0.206ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "write_fifo_in destination 3.442 ns + Shortest register " "Info: + Shortest clock path from clock \"write_fifo_in\" to destination register is 3.442 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.935 ns) 0.935 ns write_fifo_in 1 CLK PIN_J15 1 " "Info: 1: + IC(0.000 ns) + CELL(0.935 ns) = 0.935 ns; Loc. = PIN_J15; Fanout = 1; CLK Node = 'write_fifo_in'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { write_fifo_in } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.841 ns) + CELL(0.666 ns) 3.442 ns write_fifo 2 REG LCFF_X32_Y18_N23 9 " "Info: 2: + IC(1.841 ns) + CELL(0.666 ns) = 3.442 ns; Loc. = LCFF_X32_Y18_N23; Fanout = 9; REG Node = 'write_fifo'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.507 ns" { write_fifo_in write_fifo } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 1768 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.601 ns ( 46.51 % ) " "Info: Total cell delay = 1.601 ns ( 46.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.841 ns ( 53.49 % ) " "Info: Total interconnect delay = 1.841 ns ( 53.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.442 ns" { write_fifo_in write_fifo } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.442 ns" { write_fifo_in write_fifo_in~combout write_fifo } { 0.000ns 0.000ns 1.841ns } { 0.000ns 0.935ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "write_fifo_in source 3.442 ns - Longest register " "Info: - Longest clock path from clock \"write_fifo_in\" to source register is 3.442 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.935 ns) 0.935 ns write_fifo_in 1 CLK PIN_J15 1 " "Info: 1: + IC(0.000 ns) + CELL(0.935 ns) = 0.935 ns; Loc. = PIN_J15; Fanout = 1; CLK Node = 'write_fifo_in'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { write_fifo_in } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.841 ns) + CELL(0.666 ns) 3.442 ns write_fifo 2 REG LCFF_X32_Y18_N23 9 " "Info: 2: + IC(1.841 ns) + CELL(0.666 ns) = 3.442 ns; Loc. = LCFF_X32_Y18_N23; Fanout = 9; REG Node = 'write_fifo'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.507 ns" { write_fifo_in write_fifo } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 1768 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.601 ns ( 46.51 % ) " "Info: Total cell delay = 1.601 ns ( 46.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.841 ns ( 53.49 % ) " "Info: Total interconnect delay = 1.841 ns ( 53.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.442 ns" { write_fifo_in write_fifo } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.442 ns" { write_fifo_in write_fifo_in~combout write_fifo } { 0.000ns 0.000ns 1.841ns } { 0.000ns 0.935ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.442 ns" { write_fifo_in write_fifo } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.442 ns" { write_fifo_in write_fifo_in~combout write_fifo } { 0.000ns 0.000ns 1.841ns } { 0.000ns 0.935ns 0.666ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.442 ns" { write_fifo_in write_fifo } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.442 ns" { write_fifo_in write_fifo_in~combout write_fifo } { 0.000ns 0.000ns 1.841ns } { 0.000ns 0.935ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 1768 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 1768 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.316 ns" { write_fifo write_fifo~36 write_fifo~37 write_fifo } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "1.316 ns" { write_fifo write_fifo~36 write_fifo~37 write_fifo } { 0.000ns 0.437ns 0.359ns 0.000ns } { 0.000ns 0.206ns 0.206ns 0.108ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.442 ns" { write_fifo_in write_fifo } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.442 ns" { write_fifo_in write_fifo_in~combout write_fifo } { 0.000ns 0.000ns 1.841ns } { 0.000ns 0.935ns 0.666ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.442 ns" { write_fifo_in write_fifo } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.442 ns" { write_fifo_in write_fifo_in~combout write_fifo } { 0.000ns 0.000ns 1.841ns } { 0.000ns 0.935ns 0.666ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { write_fifo } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { write_fifo } {  } {  } "" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 1768 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "mainclk 201 " "Warning: Circuit may not operate. Detected 201 non-operational path(s) clocked by clock \"mainclk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "fifo_w_buf_in\[437\] fifo_w_buf\[453\] mainclk 2.315 ns " "Info: Found hold time violation between source  pin or register \"fifo_w_buf_in\[437\]\" and destination pin or register \"fifo_w_buf\[453\]\" for clock \"mainclk\" (Hold time is 2.315 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "3.047 ns + Largest " "Info: + Largest clock skew is 3.047 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mainclk destination 6.141 ns + Longest register " "Info: + Longest clock path from clock \"mainclk\" to destination register is 6.141 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns mainclk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'mainclk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { mainclk } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.000 ns) 1.357 ns mainclk~clkctrl 2 COMB CLKCTRL_G3 1047 " "Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.357 ns; Loc. = CLKCTRL_G3; Fanout = 1047; COMB Node = 'mainclk~clkctrl'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.257 ns" { mainclk mainclk~clkctrl } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.079 ns) + CELL(0.970 ns) 3.406 ns clk_5m 3 REG LCFF_X24_Y26_N1 3 " "Info: 3: + IC(1.079 ns) + CELL(0.970 ns) = 3.406 ns; Loc. = LCFF_X24_Y26_N1; Fanout = 3; REG Node = 'clk_5m'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.049 ns" { mainclk~clkctrl clk_5m } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 197 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.005 ns) + CELL(0.000 ns) 4.411 ns clk_5m~clkctrl 4 COMB CLKCTRL_G8 1138 " "Info: 4: + IC(1.005 ns) + CELL(0.000 ns) = 4.411 ns; Loc. = CLKCTRL_G8; Fanout = 1138; COMB Node = 'clk_5m~clkctrl'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.005 ns" { clk_5m clk_5m~clkctrl } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 197 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.064 ns) + CELL(0.666 ns) 6.141 ns fifo_w_buf\[453\] 5 REG LCFF_X25_Y17_N25 1 " "Info: 5: + IC(1.064 ns) + CELL(0.666 ns) = 6.141 ns; Loc. = LCFF_X25_Y17_N25; Fanout = 1; REG Node = 'fifo_w_buf\[453\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.730 ns" { clk_5m~clkctrl fifo_w_buf[453] } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 453 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.736 ns ( 44.55 % ) " "Info: Total cell delay = 2.736 ns ( 44.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.405 ns ( 55.45 % ) " "Info: Total interconnect delay = 3.405 ns ( 55.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.141 ns" { mainclk mainclk~clkctrl clk_5m clk_5m~clkctrl fifo_w_buf[453] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.141 ns" { mainclk mainclk~combout mainclk~clkctrl clk_5m clk_5m~clkctrl fifo_w_buf[453] } { 0.000ns 0.000ns 0.257ns 1.079ns 1.005ns 1.064ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mainclk source 3.094 ns - Shortest register " "Info: - Shortest clock path from clock \"mainclk\" to source register is 3.094 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns mainclk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'mainclk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { mainclk } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.000 ns) 1.357 ns mainclk~clkctrl 2 COMB CLKCTRL_G3 1047 " "Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.357 ns; Loc. = CLKCTRL_G3; Fanout = 1047; COMB Node = 'mainclk~clkctrl'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.257 ns" { mainclk mainclk~clkctrl } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.071 ns) + CELL(0.666 ns) 3.094 ns fifo_w_buf_in\[437\] 3 REG LCFF_X25_Y17_N23 1 " "Info: 3: + IC(1.071 ns) + CELL(0.666 ns) = 3.094 ns; Loc. = LCFF_X25_Y17_N23; Fanout = 1; REG Node = 'fifo_w_buf_in\[437\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.737 ns" { mainclk~clkctrl fifo_w_buf_in[437] } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 852 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.766 ns ( 57.08 % ) " "Info: Total cell delay = 1.766 ns ( 57.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.328 ns ( 42.92 % ) " "Info: Total interconnect delay = 1.328 ns ( 42.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.094 ns" { mainclk mainclk~clkctrl fifo_w_buf_in[437] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.094 ns" { mainclk mainclk~combout mainclk~clkctrl fifo_w_buf_in[437] } { 0.000ns 0.000ns 0.257ns 1.071ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.141 ns" { mainclk mainclk~clkctrl clk_5m clk_5m~clkctrl fifo_w_buf[453] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.141 ns" { mainclk mainclk~combout mainclk~clkctrl clk_5m clk_5m~clkctrl fifo_w_buf[453] } { 0.000ns 0.000ns 0.257ns 1.079ns 1.005ns 1.064ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.094 ns" { mainclk mainclk~clkctrl fifo_w_buf_in[437] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.094 ns" { mainclk mainclk~combout mainclk~clkctrl fifo_w_buf_in[437] } { 0.000ns 0.000ns 0.257ns 1.071ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 852 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.734 ns - Shortest register register " "Info: - Shortest register to register delay is 0.734 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fifo_w_buf_in\[437\] 1 REG LCFF_X25_Y17_N23 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y17_N23; Fanout = 1; REG Node = 'fifo_w_buf_in\[437\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { fifo_w_buf_in[437] } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 852 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.420 ns) + CELL(0.206 ns) 0.626 ns fifo_w_buf\[453\]~feeder 2 COMB LCCOMB_X25_Y17_N24 1 " "Info: 2: + IC(0.420 ns) + CELL(0.206 ns) = 0.626 ns; Loc. = LCCOMB_X25_Y17_N24; Fanout = 1; COMB Node = 'fifo_w_buf\[453\]~feeder'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.626 ns" { fifo_w_buf_in[437] fifo_w_buf[453]~feeder } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 453 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 0.734 ns fifo_w_buf\[453\] 3 REG LCFF_X25_Y17_N25 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.734 ns; Loc. = LCFF_X25_Y17_N25; Fanout = 1; REG Node = 'fifo_w_buf\[453\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { fifo_w_buf[453]~feeder fifo_w_buf[453] } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 453 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.314 ns ( 42.78 % ) " "Info: Total cell delay = 0.314 ns ( 42.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.420 ns ( 57.22 % ) " "Info: Total interconnect delay = 0.420 ns ( 57.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.734 ns" { fifo_w_buf_in[437] fifo_w_buf[453]~feeder fifo_w_buf[453] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "0.734 ns" { fifo_w_buf_in[437] fifo_w_buf[453]~feeder fifo_w_buf[453] } { 0.000ns 0.420ns 0.000ns } { 0.000ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 453 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.141 ns" { mainclk mainclk~clkctrl clk_5m clk_5m~clkctrl fifo_w_buf[453] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.141 ns" { mainclk mainclk~combout mainclk~clkctrl clk_5m clk_5m~clkctrl fifo_w_buf[453] } { 0.000ns 0.000ns 0.257ns 1.079ns 1.005ns 1.064ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.094 ns" { mainclk mainclk~clkctrl fifo_w_buf_in[437] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.094 ns" { mainclk mainclk~combout mainclk~clkctrl fifo_w_buf_in[437] } { 0.000ns 0.000ns 0.257ns 1.071ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.734 ns" { fifo_w_buf_in[437] fifo_w_buf[453]~feeder fifo_w_buf[453] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "0.734 ns" { fifo_w_buf_in[437] fifo_w_buf[453]~feeder fifo_w_buf[453] } { 0.000ns 0.420ns 0.000ns } { 0.000ns 0.206ns 0.108ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}