cc2420interface.tan.qmsg

对cc2420无线模块的接口。接受到的数据都使用双口ROM的方式与后台核心控制部分传送。

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "mainclk " "Info: Assuming node \"mainclk\" is an undefined clock" {  } { { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 12 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "mainclk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "write_fifo_in " "Info: Assuming node \"write_fifo_in\" is an undefined clock" {  } { { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 39 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "write_fifo_in" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "sclk_buf " "Info: Detected ripple clock \"sclk_buf\" as buffer" {  } { { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 184 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "sclk_buf" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clk_5m " "Info: Detected ripple clock \"clk_5m\" as buffer" {  } { { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 197 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_5m" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "mainclk register fifo_w_count\[0\] register si_buf 42.67 MHz 23.436 ns Internal " "Info: Clock \"mainclk\" has Internal fmax of 42.67 MHz between source register \"fifo_w_count\[0\]\" and destination register \"si_buf\" (period= 23.436 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.629 ns + Longest register register " "Info: + Longest register to register delay is 11.629 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fifo_w_count\[0\] 1 REG LCFF_X24_Y11_N17 168 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X24_Y11_N17; Fanout = 168; REG Node = 'fifo_w_count\[0\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { fifo_w_count[0] } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 1625 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.430 ns) + CELL(0.589 ns) 3.019 ns Mux12~4269 2 COMB LCCOMB_X19_Y15_N2 1 " "Info: 2: + IC(2.430 ns) + CELL(0.589 ns) = 3.019 ns; Loc. = LCCOMB_X19_Y15_N2; Fanout = 1; COMB Node = 'Mux12~4269'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.019 ns" { fifo_w_count[0] Mux12~4269 } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 652 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.357 ns) + CELL(0.206 ns) 3.582 ns Mux12~4270 3 COMB LCCOMB_X19_Y15_N22 1 " "Info: 3: + IC(0.357 ns) + CELL(0.206 ns) = 3.582 ns; Loc. = LCCOMB_X19_Y15_N22; Fanout = 1; COMB Node = 'Mux12~4270'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.563 ns" { Mux12~4269 Mux12~4270 } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 652 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.157 ns) + CELL(0.206 ns) 5.945 ns Mux12~4273 4 COMB LCCOMB_X23_Y13_N20 1 " "Info: 4: + IC(2.157 ns) + CELL(0.206 ns) = 5.945 ns; Loc. = LCCOMB_X23_Y13_N20; Fanout = 1; COMB Node = 'Mux12~4273'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.363 ns" { Mux12~4270 Mux12~4273 } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 652 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.121 ns) + CELL(0.370 ns) 7.436 ns Mux12~4296 5 COMB LCCOMB_X24_Y16_N6 1 " "Info: 5: + IC(1.121 ns) + CELL(0.370 ns) = 7.436 ns; Loc. = LCCOMB_X24_Y16_N6; Fanout = 1; COMB Node = 'Mux12~4296'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.491 ns" { Mux12~4273 Mux12~4296 } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 652 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.473 ns) + CELL(0.206 ns) 9.115 ns Mux12~4297 6 COMB LCCOMB_X22_Y12_N30 1 " "Info: 6: + IC(1.473 ns) + CELL(0.206 ns) = 9.115 ns; Loc. = LCCOMB_X22_Y12_N30; Fanout = 1; COMB Node = 'Mux12~4297'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.679 ns" { Mux12~4296 Mux12~4297 } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 652 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.615 ns) + CELL(0.651 ns) 10.381 ns Mux12~4298 7 COMB LCCOMB_X23_Y12_N18 1 " "Info: 7: + IC(0.615 ns) + CELL(0.651 ns) = 10.381 ns; Loc. = LCCOMB_X23_Y12_N18; Fanout = 1; COMB Node = 'Mux12~4298'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.266 ns" { Mux12~4297 Mux12~4298 } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 652 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.363 ns) + CELL(0.206 ns) 10.950 ns Selector22~774 8 COMB LCCOMB_X23_Y12_N0 1 " "Info: 8: + IC(0.363 ns) + CELL(0.206 ns) = 10.950 ns; Loc. = LCCOMB_X23_Y12_N0; Fanout = 1; COMB Node = 'Selector22~774'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.569 ns" { Mux12~4298 Selector22~774 } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 454 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.206 ns) 11.521 ns Selector22~776 9 COMB LCCOMB_X23_Y12_N10 1 " "Info: 9: + IC(0.365 ns) + CELL(0.206 ns) = 11.521 ns; Loc. = LCCOMB_X23_Y12_N10; Fanout = 1; COMB Node = 'Selector22~776'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.571 ns" { Selector22~774 Selector22~776 } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 454 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 11.629 ns si_buf 10 REG LCFF_X23_Y12_N11 3 " "Info: 10: + IC(0.000 ns) + CELL(0.108 ns) = 11.629 ns; Loc. = LCFF_X23_Y12_N11; Fanout = 3; REG Node = 'si_buf'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { Selector22~776 si_buf } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 453 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.748 ns ( 23.63 % ) " "Info: Total cell delay = 2.748 ns ( 23.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.881 ns ( 76.37 % ) " "Info: Total interconnect delay = 8.881 ns ( 76.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "11.629 ns" { fifo_w_count[0] Mux12~4269 Mux12~4270 Mux12~4273 Mux12~4296 Mux12~4297 Mux12~4298 Selector22~774 Selector22~776 si_buf } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "11.629 ns" { fifo_w_count[0] Mux12~4269 Mux12~4270 Mux12~4273 Mux12~4296 Mux12~4297 Mux12~4298 Selector22~774 Selector22~776 si_buf } { 0.000ns 2.430ns 0.357ns 2.157ns 1.121ns 1.473ns 0.615ns 0.363ns 0.365ns 0.000ns } { 0.000ns 0.589ns 0.206ns 0.206ns 0.370ns 0.206ns 0.651ns 0.206ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.175 ns - Smallest " "Info: - Smallest clock skew is 0.175 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mainclk destination 6.146 ns + Shortest register " "Info: + Shortest clock path from clock \"mainclk\" to destination register is 6.146 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns mainclk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'mainclk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { mainclk } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.000 ns) 1.357 ns mainclk~clkctrl 2 COMB CLKCTRL_G3 1047 " "Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.357 ns; Loc. = CLKCTRL_G3; Fanout = 1047; COMB Node = 'mainclk~clkctrl'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.257 ns" { mainclk mainclk~clkctrl } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.079 ns) + CELL(0.970 ns) 3.406 ns clk_5m 3 REG LCFF_X24_Y26_N1 3 " "Info: 3: + IC(1.079 ns) + CELL(0.970 ns) = 3.406 ns; Loc. = LCFF_X24_Y26_N1; Fanout = 3; REG Node = 'clk_5m'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.049 ns" { mainclk~clkctrl clk_5m } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 197 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.005 ns) + CELL(0.000 ns) 4.411 ns clk_5m~clkctrl 4 COMB CLKCTRL_G8 1138 " "Info: 4: + IC(1.005 ns) + CELL(0.000 ns) = 4.411 ns; Loc. = CLKCTRL_G8; Fanout = 1138; COMB Node = 'clk_5m~clkctrl'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.005 ns" { clk_5m clk_5m~clkctrl } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 197 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.069 ns) + CELL(0.666 ns) 6.146 ns si_buf 5 REG LCFF_X23_Y12_N11 3 " "Info: 5: + IC(1.069 ns) + CELL(0.666 ns) = 6.146 ns; Loc. = LCFF_X23_Y12_N11; Fanout = 3; REG Node = 'si_buf'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.735 ns" { clk_5m~clkctrl si_buf } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 453 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.736 ns ( 44.52 % ) " "Info: Total cell delay = 2.736 ns ( 44.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.410 ns ( 55.48 % ) " "Info: Total interconnect delay = 3.410 ns ( 55.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.146 ns" { mainclk mainclk~clkctrl clk_5m clk_5m~clkctrl si_buf } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.146 ns" { mainclk mainclk~combout mainclk~clkctrl clk_5m clk_5m~clkctrl si_buf } { 0.000ns 0.000ns 0.257ns 1.079ns 1.005ns 1.069ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mainclk source 5.971 ns - Longest register " "Info: - Longest clock path from clock \"mainclk\" to source register is 5.971 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns mainclk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'mainclk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { mainclk } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.000 ns) 1.357 ns mainclk~clkctrl 2 COMB CLKCTRL_G3 1047 " "Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.357 ns; Loc. = CLKCTRL_G3; Fanout = 1047; COMB Node = 'mainclk~clkctrl'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.257 ns" { mainclk mainclk~clkctrl } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.087 ns) + CELL(0.970 ns) 3.414 ns sclk_buf 3 REG LCFF_X49_Y14_N27 4 " "Info: 3: + IC(1.087 ns) + CELL(0.970 ns) = 3.414 ns; Loc. = LCFF_X49_Y14_N27; Fanout = 4; REG Node = 'sclk_buf'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.057 ns" { mainclk~clkctrl sclk_buf } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 184 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.828 ns) + CELL(0.000 ns) 4.242 ns sclk_buf~clkctrl 4 COMB CLKCTRL_G7 34 " "Info: 4: + IC(0.828 ns) + CELL(0.000 ns) = 4.242 ns; Loc. = CLKCTRL_G7; Fanout = 34; COMB Node = 'sclk_buf~clkctrl'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.828 ns" { sclk_buf sclk_buf~clkctrl } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 184 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.063 ns) + CELL(0.666 ns) 5.971 ns fifo_w_count\[0\] 5 REG LCFF_X24_Y11_N17 168 " "Info: 5: + IC(1.063 ns) + CELL(0.666 ns) = 5.971 ns; Loc. = LCFF_X24_Y11_N17; Fanout = 168; REG Node = 'fifo_w_count\[0\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.729 ns" { sclk_buf~clkctrl fifo_w_count[0] } "NODE_NAME" } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 1625 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.736 ns ( 45.82 % ) " "Info: Total cell delay = 2.736 ns ( 45.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.235 ns ( 54.18 % ) " "Info: Total interconnect delay = 3.235 ns ( 54.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.971 ns" { mainclk mainclk~clkctrl sclk_buf sclk_buf~clkctrl fifo_w_count[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.971 ns" { mainclk mainclk~combout mainclk~clkctrl sclk_buf sclk_buf~clkctrl fifo_w_count[0] } { 0.000ns 0.000ns 0.257ns 1.087ns 0.828ns 1.063ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.146 ns" { mainclk mainclk~clkctrl clk_5m clk_5m~clkctrl si_buf } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.146 ns" { mainclk mainclk~combout mainclk~clkctrl clk_5m clk_5m~clkctrl si_buf } { 0.000ns 0.000ns 0.257ns 1.079ns 1.005ns 1.069ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.971 ns" { mainclk mainclk~clkctrl sclk_buf sclk_buf~clkctrl fifo_w_count[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.971 ns" { mainclk mainclk~combout mainclk~clkctrl sclk_buf sclk_buf~clkctrl fifo_w_count[0] } { 0.000ns 0.000ns 0.257ns 1.087ns 0.828ns 1.063ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 1625 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 453 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 1625 -1 0 } } { "cc2420interface.vhd" "" { Text "D:/我的文档/vhdl design/cc2420interface/cc2420interface.vhd" 453 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "11.629 ns" { fifo_w_count[0] Mux12~4269 Mux12~4270 Mux12~4273 Mux12~4296 Mux12~4297 Mux12~4298 Selector22~774 Selector22~776 si_buf } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "11.629 ns" { fifo_w_count[0] Mux12~4269 Mux12~4270 Mux12~4273 Mux12~4296 Mux12~4297 Mux12~4298 Selector22~774 Selector22~776 si_buf } { 0.000ns 2.430ns 0.357ns 2.157ns 1.121ns 1.473ns 0.615ns 0.363ns 0.365ns 0.000ns } { 0.000ns 0.589ns 0.206ns 0.206ns 0.370ns 0.206ns 0.651ns 0.206ns 0.206ns 0.108ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.146 ns" { mainclk mainclk~clkctrl clk_5m clk_5m~clkctrl si_buf } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.146 ns" { mainclk mainclk~combout mainclk~clkctrl clk_5m clk_5m~clkctrl si_buf } { 0.000ns 0.000ns 0.257ns 1.079ns 1.005ns 1.069ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.971 ns" { mainclk mainclk~clkctrl sclk_buf sclk_buf~clkctrl fifo_w_count[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.971 ns" { mainclk mainclk~combout mainclk~clkctrl sclk_buf sclk_buf~clkctrl fifo_w_count[0] } { 0.000ns 0.000ns 0.257ns 1.087ns 0.828ns 1.063ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}