cc2420interface.map.rpt

对cc2420无线模块的接口。接受到的数据都使用双口ROM的方式与后台核心控制部分传送。

Analysis & Synthesis report for cc2420interface
Fri Aug 29 23:38:23 2008
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. State Machine - |cc2420interface|current_state
  9. State Machine - |cc2420interface|next_state
 10. Registers Removed During Synthesis
 11. General Register Statistics
 12. Inverted Register Statistics
 13. Multiplexer Restructuring Statistics (Restructuring Performed)
 14. Source assignments for altsyncram:Mux11_rtl_0|altsyncram_e301:auto_generated
 15. Parameter Settings for Inferred Entity Instance: altsyncram:Mux11_rtl_0
 16. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                 ;
+------------------------------------+-----------------------------------------+
; Analysis & Synthesis Status        ; Successful - Fri Aug 29 23:38:23 2008   ;
; Quartus II Version                 ; 7.0 Build 33 02/05/2007 SJ Full Version ;
; Revision Name                      ; cc2420interface                         ;
; Top-level Entity Name              ; cc2420interface                         ;
; Family                             ; Cyclone II                              ;
; Total logic elements               ; 2,219                                   ;
;     Total combinational functions  ; 2,219                                   ;
;     Dedicated logic registers      ; 2,212                                   ;
; Total registers                    ; N/A until Partition Merge               ;
; Total pins                         ; N/A until Partition Merge               ;
; Total virtual pins                 ; N/A until Partition Merge               ;
; Total memory bits                  ; N/A until Partition Merge               ;
; Embedded Multiplier 9-bit elements ; N/A until Partition Merge               ;
; Total PLLs                         ; N/A until Partition Merge               ;
+------------------------------------+-----------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Option                                                             ; Setting            ; Default Value      ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Device                                                             ; EP2C20F484C8       ;                    ;
; Top-level entity name                                              ; cc2420interface    ; cc2420interface    ;
; Family name                                                        ; Cyclone II         ; Stratix            ;
; Restructure Multiplexers                                           ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                ; Off                ; Off                ;
; Preserve fewer node names                                          ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                          ; Off                ; Off                ;
; Verilog Version                                                    ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                       ; VHDL93             ; VHDL93             ;
; State Machine Processing                                           ; Auto               ; Auto               ;
; Safe State Machine                                                 ; Off                ; Off                ;
; Extract Verilog State Machines                                     ; On                 ; On                 ;
; Extract VHDL State Machines                                        ; On                 ; On                 ;
; Ignore Verilog initial constructs                                  ; Off                ; Off                ;
; Add Pass-Through Logic to Inferred RAMs                            ; On                 ; On                 ;
; DSP Block Balancing                                                ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                 ; On                 ; On                 ;
; Power-Up Don't Care                                                ; On                 ; On                 ;
; Remove Redundant Logic Cells                                       ; Off                ; Off                ;
; Remove Duplicate Registers                                         ; On                 ; On                 ;
; Ignore CARRY Buffers                                               ; Off                ; Off                ;
; Ignore CASCADE Buffers                                             ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                              ; Off                ; Off                ;