cc2420interface.fit.rpt

对cc2420无线模块的接口。接受到的数据都使用双口ROM的方式与后台核心控制部分传送。

; Router Timing Optimization Level                       ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                            ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                               ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                                   ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                            ; Off                            ; Off                            ;
; PowerPlay Power Optimization                           ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                        ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing             ; On                             ; On                             ;
; Limit to One Fitting Attempt                           ; Off                            ; Off                            ;
; Final Placement Optimizations                          ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations            ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                          ; 1                              ; 1                              ;
; PCI I/O                                                ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                  ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                              ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                     ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/III/Cyclone II/III ; Auto                           ; Auto                           ;
; Auto Delay Chains                                      ; On                             ; On                             ;
; Auto Merge PLLs                                        ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                      ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic     ; Off                            ; Off                            ;
; Perform Register Duplication                           ; Off                            ; Off                            ;
; Perform Register Retiming                              ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                 ; Off                            ; Off                            ;
; Fitter Effort                                          ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                        ; Normal                         ; Normal                         ;
; Auto Global Clock                                      ; On                             ; On                             ;
; Auto Global Register Control Signals                   ; On                             ; On                             ;
; Stop After Congestion Map Generation                   ; Off                            ; Off                            ;
; Use smart compilation                                  ; Off                            ; Off                            ;
+--------------------------------------------------------+--------------------------------+--------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Netlist Optimizations                                                                                                                                               ;
+-------------------+-----------------+------------------+---------------------+-----------+--------------------------------------------------------------+------------------+
; Node              ; Action          ; Operation        ; Reason              ; Node Port ; Destination Node                                             ; Destination Port ;
+-------------------+-----------------+------------------+---------------------+-----------+--------------------------------------------------------------+------------------+
; start_add_buf[3]  ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; altsyncram:Mux11_rtl_0|altsyncram_e301:auto_generated|q_a[0] ; PORTADATAOUT     ;
; start_add_buf[4]  ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; altsyncram:Mux11_rtl_0|altsyncram_e301:auto_generated|q_a[1] ; PORTADATAOUT     ;
; start_add_buf[5]  ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; altsyncram:Mux11_rtl_0|altsyncram_e301:auto_generated|q_a[2] ; PORTADATAOUT     ;
; start_add_buf[6]  ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; altsyncram:Mux11_rtl_0|altsyncram_e301:auto_generated|q_a[3] ; PORTADATAOUT     ;
; start_add_buf[7]  ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; altsyncram:Mux11_rtl_0|altsyncram_e301:auto_generated|q_a[4] ; PORTADATAOUT     ;
; start_add_buf[8]  ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; altsyncram:Mux11_rtl_0|altsyncram_e301:auto_generated|q_a[5] ; PORTADATAOUT     ;
; start_add_buf[9]  ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; altsyncram:Mux11_rtl_0|altsyncram_e301:auto_generated|q_a[6] ; PORTADATAOUT     ;
; start_add_buf[10] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; altsyncram:Mux11_rtl_0|altsyncram_e301:auto_generated|q_a[7] ; PORTADATAOUT     ;
; start_add_buf[11] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; altsyncram:Mux11_rtl_0|altsyncram_e301:auto_generated|q_a[8] ; PORTADATAOUT     ;
; start_add_buf[12] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; altsyncram:Mux11_rtl_0|altsyncram_e301:auto_generated|q_a[9] ; PORTADATAOUT     ;
+-------------------+-----------------+------------------+---------------------+-----------+--------------------------------------------------------------+------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in D:/我的文档/vhdl design/cc2420interface/cc2420interface.pin.


+------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                          ;
+---------------------------------------------+--------------------------+
; Resource                                    ; Usage                    ;
+---------------------------------------------+--------------------------+
; Total logic elements                        ; 3,682 / 18,752 ( 20 % )  ;
;     -- Combinational with no register       ; 1480                     ;
;     -- Register only                        ; 1463                     ;
;     -- Combinational with a register        ; 739                      ;
;                                             ;                          ;
; Logic element usage by number of LUT inputs ;                          ;
;     -- 4 input functions                    ; 1513                     ;
;     -- 3 input functions                    ; 155                      ;
;     -- <=2 input functions                  ; 551                      ;
;     -- Register only                        ; 1463                     ;
;                                             ;                          ;
; Logic elements by mode                      ;                          ;
;     -- normal mode                          ; 1887                     ;
;     -- arithmetic mode                      ; 332                      ;
;                                             ;                          ;
; Total registers*                            ; 2,202 / 19,649 ( 11 % )  ;
;     -- Dedicated logic registers            ; 2,202 / 18,752 ( 12 % )  ;
;     -- I/O registers                        ; 0 / 897 ( 0 % )          ;
;                                             ;                          ;
; Total LABs:  partially or completely used   ; 264 / 1,172 ( 23 % )     ;
; User inserted logic elements                ; 0                        ;
; Virtual pins                                ; 0                        ;
; I/O pins                                    ; 63 / 315 ( 20 % )        ;
;     -- Clock pins                           ; 1 / 8 ( 13 % )           ;
; Global signals                              ; 16                       ;
; M4Ks                                        ; 1 / 52 ( 2 % )           ;
; Total memory bits                           ; 2,560 / 239,616 ( 1 % )  ;
; Total RAM block bits                        ; 4,608 / 239,616 ( 2 % )  ;
; Embedded Multiplier 9-bit elements          ; 0 / 52 ( 0 % )           ;