writeram.v

Fusion中的双口RAM编写

// writeram.v
module writeram(key,RI,clk,rst,Waddress,TI,Raddress,sendwr);

input         key;             //按键
input         clk;             //时钟
input         RI;              //接收中断
input         TI;              //发送中断
output        sendwr;          //发送模块写信号
output        rst;             
output [10:0] Waddress;        //写数据地址
output [10:0] Raddress;        //读数据地址 

parameter   wrcntbit=11;
parameter   rdcntbit=11;

reg [10:0]  Waddress;          //写地址
reg [10:0]  Raddress;          //读地址

reg         rst_reg;
reg [15:0]  count;

reg [wrcntbit-1:0] wrcnt;
reg [rdcntbit-1:0] rdcnt;

wire      key_buff;
reg       bit0,bit1,bit2;

wire      rst_posedge,rst_negedge;
reg       rst_buff;

wire      RI_negedge;
reg       RI_buff;

wire        sendclk;
reg [15:0]  sendclkdiv;

wire        TI_posedge;
reg         TI_buff;

reg         rst1,rst2,rst3,rst4,rst5;

//下面产生写地址复位信号rst，同时该信号也是单片机复位信号，存储器的读写周期指示信号
assign rst = rst_reg;

always @(posedge clk)
begin
    count <= count + 1'b1;
end

assign key_buff = bit0 & bit1 & bit2;
always@( posedge count[15])
begin
    bit0 <= key;
    bit1 <= bit0;
    bit2 <= bit1;
end
//assign key_negedge = key_buff & (~key);
always@(posedge key_buff)
begin
    rst_reg <= ~rst_reg;
end

//写地址处理进程
always@(posedge clk)
begin
   rst_buff<=rst_reg;
end
always@(posedge clk)
begin
    RI_buff <= RI;
end
assign rst_negedge = (~rst_reg) & rst_buff;
assign RI_negedge = (~RI) & RI_buff;
always@(posedge clk)
begin
  if(rst_negedge)
   begin
     Waddress <= 11'b11111111111;
     wrcnt <= 0;
   end
   else if(RI_negedge)//else if(RI_negedge&&(rst_reg==0))
      begin
        Waddress <= Waddress+11'd1;
        wrcnt <= wrcnt+1'b1;
   end

end

//下读地址发生进程
always@(posedge clk)
begin
    TI_buff<=TI;
end
assign rst_posedge = rst_reg&(~rst_buff);
assign TI_posedge = (TI)&(~TI_buff);
always@(posedge clk)
begin
   if(rst_posedge)
   begin
   Raddress <= 0;
   rdcnt <= 0;
   end
   else if(TI_posedge)
   begin
   Raddress <= Raddress+1;
   rdcnt <= rdcnt+1'b1;
   end
end

//sendclk产生进程
assign sendclk =(sendclkdiv == 16'd65535);
always@(posedge clk)
begin
  if(sendclk)
    sendclkdiv = 0;
  else 
    sendclkdiv = sendclkdiv + 16'd1;
end

//产生sendwr信号
assign sendwr = rst5 & sendclk & ((rdcnt!= wrcnt));


//产生rst延迟5个时钟rst5信号
always@(posedge clk)
begin
    rst1 <= rst;
    rst2 <= rst1;
    rst3 <= rst2;
    rst4 <= rst3;
    rst5 <= rst4;
end

//

endmodule