flashmemory_top.v

Fusion的Flash memory测试

// main.v

`timescale 1 ns/100 ps

module FlashMemory_top(CLK48M,rst,outdata);

input CLK48M,rst;                           //时钟复位信号

output  [7:0] outdata;                      //数据输出						
reg     [7:0] outdata;
reg     READ_EN,WRITE_EN;                   //读写使能
reg     [7:0]DATA_IN;                       //数据输入
reg     [17:0]addr1,addr2;                  //读地址，写地址
reg     PROGRAM_EN;                         //编程使能信号
reg     flag_r;                             //读标志
reg     [1:0]state1;                         //状态选择
reg     [2:0]state2;
reg     NEXT;                               
wire    CLK1M;
wire    BUSY;
wire    [17:0] ADDRES;                      //地址信号
wire    READ,WRITE;
wire    [7:0] DATAOUT;
wire    PROGRAM;
wire    [7:0]DATAIN;
wire    READ_NEXT;
assign  READ_NEXT=NEXT;                     //预读信号   
assign  ADDRES=flag_r?addr1:addr2;          //地址选择信号
assign  READ=READ_EN;                       //读使能信号
assign  WRITE=WRITE_EN;                     //写使能信号
assign  PROGRAM=PROGRAM_EN;                 //编程使能
assign  DATAIN=DATA_IN;                     //数据输入

parameter IDLE1=2'b01,                       //读状态
          C_ADDR=2'b10,
          RD_DATA=2'b11;

parameter IDLE2=3'b001,                      //写状态
          WR_DATA=3'b010,
          PROGRAM_DATA=3'b011,
          WR_OVER=3'b100,
          WAIT_STATE=3'b101;                  
always @(posedge CLK1M or posedge rst)                   //读进程
  begin
    if(rst)
        begin
        state1<=IDLE1;
        addr1<=18'd0;
        READ_EN<=1'b0;
        NEXT<=1'b0;
        end
    else
    case(state1)
      IDLE1:                              //初始化状态
        if(flag_r)                               
          begin
            state1<=C_ADDR;
            addr1<=18'd0;
            NEXT<=1'b1;                   //开启预读模式
            READ_EN<=1'b1;                 //读使能开                
          end
        else
          begin
            state1<=IDLE1;
            READ_EN<=1'b0;
          end                
      C_ADDR:                             //生成地址
        if(addr1==18'd50)
          begin
            addr1<=18'd0;
          end
        else if(!BUSY)                   //如果不时忙状态开始读
            begin
            addr1<=addr1+1'b1;
            state1<=C_ADDR;    
            end             
    default:state1<=IDLE1;
  endcase
end
always @(posedge CLK1M)
    begin
        outdata<=DATAOUT;
    end

always @ (posedge CLK1M or posedge rst)          //写进程?

begin
  if(rst)
     begin
        state2<=IDLE2;
        WRITE_EN<=1'b0;
        flag_r<=1'b0;      
     end  
  else  
     case(state2)             
      IDLE2:                                    //初始化状态
        begin
          WRITE_EN<=1'b1;
          addr2<=18'd0;
          DATA_IN<=8'd0;
          PROGRAM_EN<=1'b0;                          
          state2<=WR_DATA;                   
        end

       WR_DATA:                                  //写数据状态
          if(!BUSY)                             //判断如果不忙
            begin
              if(addr2==18'd50)
                begin
                  WRITE_EN<=1'b0;               //写完毕关写使能
                  state2<=PROGRAM_DATA;
                end           
              else 
                begin 
                  addr2<=addr2+1'b1;          //地址不断加1变化
                  DATA_IN<=DATA_IN+1'b1;      //数据不断变化
                  state2<=WR_DATA;
                end
            end
          else
             state2<=WR_DATA;

      PROGRAM_DATA:                             //编程数据
          if(!BUSY)
            begin
              PROGRAM_EN<=1'b1;                 //开编程使能
              addr2<=18'd0;                     //定义编程地址
              state2<=WR_OVER;
            end
          else
              state2<=PROGRAM_DATA;       
      WR_OVER:                                  //结束状态
        if(!BUSY)
          begin
            PROGRAM_EN<=1'b0;                   //关编程信号
            flag_r<=1'b1;
            state2<=WAIT_STATE;
          end
        else
          begin  
          PROGRAM_EN<=1'b0;
          flag_r<=1'b0;
          state2<=WR_OVER;
          end

      WAIT_STATE: state2<=WAIT_STATE;

      default: state2<=IDLE2;

    endcase
end


PLL_1M PLL_1M_0(
               .POWERDOWN(1'b1),
               .CLKA(CLK48M),
               .GLA(CLK1M)
               );

data data_0(                            //例化一个FlashMemory

       .USER_CLK(CLK1M),
       .USER_RESET(!rst),   

       .USER_ADD(ADDRES),

       .USER_AUX_BLOCK(1'b0),
       .USER_DATA(DATAIN),
       .USER_DISCARD_PAGE(1'b0),
       .USER_ERASE_PAGE(1'b0),
       .USER_OVERWRITE_PAGE(1'b0),
       .USER_OVERWRITE_PROT(1'b0),
       .USER_PAGELOSS_PROT(1'b0),
       .USER_PROGRAM(PROGRAM),

       .USER_READ(READ),
       .USER_READ_NEXT(READ_NEXT),
       .USER_LOCK(1'b0),

       .USER_SPARE_PAGE(1'b0),
       .USER_UNPROT_PAGE(1'b0),

       .USER_WIDTH(2'b00),

       .USER_WRITE(WRITE),

       .USER_DOUT(DATAOUT),

       .USER_PAGE_STATUS(1'b0),
       .USER_NVM_STATUS(),
       .USER_NVM_BUSY(BUSY)
    );

endmodule