pll_res.cfg

来自「半带插值滤波器设计、综合、仿真和硬件测试」· CFG 代码 · 共 49 行

Synthesizing
Nominal fin 8000 ps (125 MHz)
Requested bandwidth auto
F Zero 0 Khz
F Bandwidth 0 Khz
F Pole 0 Khz
Lock range 0-0 ps (0-0 MHz)
not using reconfig

tap 0   mult  1  div   1  duty  50  phase 0  delay 0
tap 1   mult  2  div   1  duty  50  phase 0  delay 0

CPU time used for synthesis 171 ms.
SUCCESS

Internal View
M 4
N 1
M_delay 0
N_delay 0
M0   1
VCO  0
VCO min 1000 VCO max 2000 VCO center 1333
PFD min 1500 PFD max 333333 VCO gain 1500
i      50
c_high 10
r      1020.5
Phase degree resolution 11.25
 tap phase min/max degree (duty cycle resolution) 
-180 180 (12.5)
-180 180 (25)


tap 0   count 4  high  2  low   2  even  1  bypass 0  init  1  vco   0  delay 0  max_count 512
tap 1   count 2  high  1  low   1  even  1  bypass 0  init  1  vco   0  delay 0  max_count 512

Real User Properties
Nominal fin 8000 ps (125 MHz)
Requested bandwidth auto
F Zero 1507.56 Khz
F Bandwidth 3046.88 Khz
F Pole 99498.7 Khz
Lock range 4000-8000 ps (125-250 MHz)
not using reconfig

tap 0   mult  1  div   1  duty  50  phase 0  delay 0
tap 1   mult  2  div   1  duty  50  phase 0  delay 0