clock_gen.v

用ＦＰＧＡ对ＬＣＤ进行控制

// Clock_Gen.v

/****************为LCD_Drvier模块产生500Hz的时钟信号**************/

module Clock_Gen(clk_48M,rst,clk_LCD);

input   clk_48M,rst;                //rst为全局复位信号（高电平有效）              
output  clk_LCD;   

wire    clk_counter;
reg     [9:0] count;
reg     clk_BUF;


PLL_1M      U1(.POWERDOWN(1'b1),    //调用PLL模块对48M晶振进行分频
               .CLKA(clk_48M),
               .GLA(clk_counter));  //clk_counter为1M时钟输出
               
always @(posedge clk_counter or posedge rst)
begin                                   //利用计数器分频产生500Hz时钟
    if(rst)
        begin 
            clk_BUF <= 1'b0;
            count <= 10'b0;
        end
    else
    begin   
        if(count == 10'd1000) 
            begin
                clk_BUF <= ~clk_BUF;
                count <= 10'b0;
            end     
        else
            begin
                clk_BUF <= clk_BUF;     //clk_BUF为500Hz的时钟信号
                count <= count + 1'b1;
            end
    end
end

assign  clk_LCD = clk_BUF;
//clk_LCD为LCD_Drvier模块所需要的500Hz的时钟信号

endmodule