32时隙分割源代码.txt

32时隙的VHDL源代码 在开发E1 2M线路的时候非常有用

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


ENTITY Ts01 IS
PORT( clk, data, reset: IN STD_LOGIC;
      floss:OUT STD_LOGIC) ;
END Ts01;

ARCHITECTURE behavior OF Ts01 IS
SIGNAL seaway: STD_LOGIC;
SIGNAL even: STD_LOGIC;
SIGNAL odd: STD_LOGIC;
SIGNAL q: STD_LOGIC_VECTOR (7 DOWNTO 0) ;
BEGIN
PROCESS( clk)
VARIABLE counter: INTEGER;
VARIABLE keep: INTEGER;
VARIABLE loss: INTEGER;
BEGIN
IF ( reset = '1') THEN 
floss <= '0'; 
seaway <= '0'; 
even <='0';
odd <= '0'; 
q <= "00000000" ;
ELSIF ( clk'EVENT AND clk = '1') THEN
q (7) <= q (6) ;
q (6) <= q (5) ;
q (5) <= q (4) ;
q (4) <= q (3) ;
q (3) <= q (2) ;
q (2) <= q (1) ;
q (1) <= q (0) ;
q (0) <= data;
IF ( seaway = '0') THEN
IF ( q = "10011011" ) THEN
counter := 8; 
keep := 1;
loss := 0;
seaway <= '1'; 
even <= '0';
odd <= '1'; 
END IF;
ELSE 
counter := counter + 1;
IF ( counter = 256) THEN
counter := 0;
ELSIF ( counter = 8) THEN
IF ( even = '1'AND odd = '0') THEN 
IF ( q = "10011011" ) THEN
keep := keep + 1;
IF ( loss <= 3) THEN
loss := 0;
END IF;
IF ( keep >= 3) THEN
keep := 3;
floss <= '1'; 
ELSE
floss <= '0';
END IF;
ELSE
loss := loss + 1;
IF ( keep <= 2) THEN
keep := 0;
seaway <= '0';
floss <= '0';
ELSE
keep := 3;
END IF;
IF ( loss = 4) THEN
floss <= '0';
keep := 0;
seaway <= '0';
END IF;
END IF;
even <= '0';
odd <= '1';
ELSIF ( even = '0'AND odd = '1') THEN
IF ( q (7 DOWNTO 5) = "110" ) THEN
keep := keep + 1;
IF ( keep >= 3) THEN
keep := 3;
floss <='1';
ELSE
floss <= '0';
END IF;
IF ( loss <= 3) THEN
loss := 0;
END IF;
ELSE
loss := loss + 1;
IF ( keep <= 2) THEN
keep := 0;
seaway <= '0';
floss <= '0';
ELSE
keep := 3;
END IF;
IF ( loss = 4) THEN
floss <= '0';
keep := 0;
seaway <='0';
END IF;
END IF;
even <= '1';
odd <= '0';
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END behavior;