pro3.tan.qmsg

VHDL语言编写的 SPI总线控制器。。

{ "Info" "ITDB_FULL_TPD_RESULT" "ssl mosi 9.061 ns Longest " "Info: Longest tpd from source pin \"ssl\" to destination pin \"mosi\" is 9.061 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns ssl 1 PIN PIN_121 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_121; Fanout = 1; PIN Node = 'ssl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "" { ssl } "NODE_NAME" } "" } } { "pro5.bdf" "" { Schematic "C:/altera/quartus51/my project/pro3/pro5.bdf" { { 224 48 216 240 "ssl" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.518 ns) + CELL(2.074 ns) 9.061 ns mosi 2 PIN PIN_124 0 " "Info: 2: + IC(5.518 ns) + CELL(2.074 ns) = 9.061 ns; Loc. = PIN_124; Fanout = 0; PIN Node = 'mosi'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "7.592 ns" { ssl mosi } "NODE_NAME" } "" } } { "pro5.bdf" "" { Schematic "C:/altera/quartus51/my project/pro3/pro5.bdf" { { 272 512 688 288 "mosi" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.543 ns ( 39.10 % ) " "Info: Total cell delay = 3.543 ns ( 39.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.518 ns ( 60.90 % ) " "Info: Total interconnect delay = 5.518 ns ( 60.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "9.061 ns" { ssl mosi } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "9.061 ns" { ssl ssl~out0 mosi } { 0.000ns 0.000ns 5.518ns } { 0.000ns 1.469ns 2.074ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "sipo:inst1\|q\[0\] miso clk -0.678 ns register " "Info: th for register \"sipo:inst1\|q\[0\]\" (data pin = \"miso\", clock pin = \"clk\") is -0.678 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.814 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.814 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_122 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_122; Fanout = 16; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "" { clk } "NODE_NAME" } "" } } { "pro5.bdf" "" { Schematic "C:/altera/quartus51/my project/pro3/pro5.bdf" { { 184 48 216 200 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.634 ns) + CELL(0.711 ns) 7.814 ns sipo:inst1\|q\[0\] 2 REG LC_X34_Y20_N8 2 " "Info: 2: + IC(5.634 ns) + CELL(0.711 ns) = 7.814 ns; Loc. = LC_X34_Y20_N8; Fanout = 2; REG Node = 'sipo:inst1\|q\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "6.345 ns" { clk sipo:inst1|q[0] } "NODE_NAME" } "" } } { "sipo.vhd" "" { Text "C:/altera/quartus51/my project/pro3/sipo.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 27.90 % ) " "Info: Total cell delay = 2.180 ns ( 27.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.634 ns ( 72.10 % ) " "Info: Total interconnect delay = 5.634 ns ( 72.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "7.814 ns" { clk sipo:inst1|q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.814 ns" { clk clk~out0 sipo:inst1|q[0] } { 0.000ns 0.000ns 5.634ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "sipo.vhd" "" { Text "C:/altera/quartus51/my project/pro3/sipo.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.507 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.507 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns miso 1 PIN PIN_123 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_123; Fanout = 1; PIN Node = 'miso'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "" { miso } "NODE_NAME" } "" } } { "pro5.bdf" "" { Schematic "C:/altera/quartus51/my project/pro3/pro5.bdf" { { 96 48 216 112 "miso" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.729 ns) + CELL(0.309 ns) 8.507 ns sipo:inst1\|q\[0\] 2 REG LC_X34_Y20_N8 2 " "Info: 2: + IC(6.729 ns) + CELL(0.309 ns) = 8.507 ns; Loc. = LC_X34_Y20_N8; Fanout = 2; REG Node = 'sipo:inst1\|q\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "7.038 ns" { miso sipo:inst1|q[0] } "NODE_NAME" } "" } } { "sipo.vhd" "" { Text "C:/altera/quartus51/my project/pro3/sipo.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.778 ns ( 20.90 % ) " "Info: Total cell delay = 1.778 ns ( 20.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.729 ns ( 79.10 % ) " "Info: Total interconnect delay = 6.729 ns ( 79.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "8.507 ns" { miso sipo:inst1|q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.507 ns" { miso miso~out0 sipo:inst1|q[0] } { 0.000ns 0.000ns 6.729ns } { 0.000ns 1.469ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "7.814 ns" { clk sipo:inst1|q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.814 ns" { clk clk~out0 sipo:inst1|q[0] } { 0.000ns 0.000ns 5.634ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "8.507 ns" { miso sipo:inst1|q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.507 ns" { miso miso~out0 sipo:inst1|q[0] } { 0.000ns 0.000ns 6.729ns } { 0.000ns 1.469ns 0.309ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jul 31 23:24:56 2006 " "Info: Processing ended: Mon Jul 31 23:24:56 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}