pro3.tan.qmsg

VHDL语言编写的 SPI总线控制器。。

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "pro5.bdf" "" { Schematic "C:/altera/quartus51/my project/pro3/pro5.bdf" { { 184 48 216 200 "clk" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "load " "Info: Assuming node \"load\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "pro5.bdf" "" { Schematic "C:/altera/quartus51/my project/pro3/pro5.bdf" { { 288 48 216 304 "load" "" } } } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register sopi:inst\|q\[1\] sopi:inst\|q\[2\] 275.03 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 275.03 MHz between source register \"sopi:inst\|q\[1\]\" and destination register \"sopi:inst\|q\[2\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.495 ns + Longest register register " "Info: + Longest register to register delay is 1.495 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sopi:inst\|q\[1\] 1 REG LC_X34_Y2_N5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y2_N5; Fanout = 1; REG Node = 'sopi:inst\|q\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "" { sopi:inst|q[1] } "NODE_NAME" } "" } } { "sopi.vhd" "" { Text "C:/altera/quartus51/my project/pro3/sopi.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.757 ns) + CELL(0.738 ns) 1.495 ns sopi:inst\|q\[2\] 2 REG LC_X34_Y2_N8 1 " "Info: 2: + IC(0.757 ns) + CELL(0.738 ns) = 1.495 ns; Loc. = LC_X34_Y2_N8; Fanout = 1; REG Node = 'sopi:inst\|q\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "1.495 ns" { sopi:inst|q[1] sopi:inst|q[2] } "NODE_NAME" } "" } } { "sopi.vhd" "" { Text "C:/altera/quartus51/my project/pro3/sopi.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.738 ns ( 49.36 % ) " "Info: Total cell delay = 0.738 ns ( 49.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.757 ns ( 50.64 % ) " "Info: Total interconnect delay = 0.757 ns ( 50.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "1.495 ns" { sopi:inst|q[1] sopi:inst|q[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.495 ns" { sopi:inst|q[1] sopi:inst|q[2] } { 0.000ns 0.757ns } { 0.000ns 0.738ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.766 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 7.766 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_122 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_122; Fanout = 16; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "" { clk } "NODE_NAME" } "" } } { "pro5.bdf" "" { Schematic "C:/altera/quartus51/my project/pro3/pro5.bdf" { { 184 48 216 200 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.586 ns) + CELL(0.711 ns) 7.766 ns sopi:inst\|q\[2\] 2 REG LC_X34_Y2_N8 1 " "Info: 2: + IC(5.586 ns) + CELL(0.711 ns) = 7.766 ns; Loc. = LC_X34_Y2_N8; Fanout = 1; REG Node = 'sopi:inst\|q\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "6.297 ns" { clk sopi:inst|q[2] } "NODE_NAME" } "" } } { "sopi.vhd" "" { Text "C:/altera/quartus51/my project/pro3/sopi.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 28.07 % ) " "Info: Total cell delay = 2.180 ns ( 28.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.586 ns ( 71.93 % ) " "Info: Total interconnect delay = 5.586 ns ( 71.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "7.766 ns" { clk sopi:inst|q[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.766 ns" { clk clk~out0 sopi:inst|q[2] } { 0.000ns 0.000ns 5.586ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.766 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.766 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_122 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_122; Fanout = 16; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "" { clk } "NODE_NAME" } "" } } { "pro5.bdf" "" { Schematic "C:/altera/quartus51/my project/pro3/pro5.bdf" { { 184 48 216 200 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.586 ns) + CELL(0.711 ns) 7.766 ns sopi:inst\|q\[1\] 2 REG LC_X34_Y2_N5 1 " "Info: 2: + IC(5.586 ns) + CELL(0.711 ns) = 7.766 ns; Loc. = LC_X34_Y2_N5; Fanout = 1; REG Node = 'sopi:inst\|q\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "6.297 ns" { clk sopi:inst|q[1] } "NODE_NAME" } "" } } { "sopi.vhd" "" { Text "C:/altera/quartus51/my project/pro3/sopi.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 28.07 % ) " "Info: Total cell delay = 2.180 ns ( 28.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.586 ns ( 71.93 % ) " "Info: Total interconnect delay = 5.586 ns ( 71.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "7.766 ns" { clk sopi:inst|q[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.766 ns" { clk clk~out0 sopi:inst|q[1] } { 0.000ns 0.000ns 5.586ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "7.766 ns" { clk sopi:inst|q[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.766 ns" { clk clk~out0 sopi:inst|q[2] } { 0.000ns 0.000ns 5.586ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "7.766 ns" { clk sopi:inst|q[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.766 ns" { clk clk~out0 sopi:inst|q[1] } { 0.000ns 0.000ns 5.586ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "sopi.vhd" "" { Text "C:/altera/quartus51/my project/pro3/sopi.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "sopi.vhd" "" { Text "C:/altera/quartus51/my project/pro3/sopi.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "1.495 ns" { sopi:inst|q[1] sopi:inst|q[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.495 ns" { sopi:inst|q[1] sopi:inst|q[2] } { 0.000ns 0.757ns } { 0.000ns 0.738ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "7.766 ns" { clk sopi:inst|q[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.766 ns" { clk clk~out0 sopi:inst|q[2] } { 0.000ns 0.000ns 5.586ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "7.766 ns" { clk sopi:inst|q[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.766 ns" { clk clk~out0 sopi:inst|q[1] } { 0.000ns 0.000ns 5.586ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "" { sopi:inst|q[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { sopi:inst|q[2] } {  } {  } } } { "sopi.vhd" "" { Text "C:/altera/quartus51/my project/pro3/sopi.vhd" 15 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "sopi:inst\|q\[0\] data_in\[0\] load 5.226 ns register " "Info: tsu for register \"sopi:inst\|q\[0\]\" (data pin = \"data_in\[0\]\", clock pin = \"load\") is 5.226 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.149 ns + Longest pin register " "Info: + Longest pin to register delay is 7.149 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns data_in\[0\] 1 PIN PIN_119 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_119; Fanout = 1; PIN Node = 'data_in\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "" { data_in[0] } "NODE_NAME" } "" } } { "pro5.bdf" "" { Schematic "C:/altera/quartus51/my project/pro3/pro5.bdf" { { 304 48 216 320 "data_in\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.084 ns) + CELL(0.590 ns) 7.149 ns sopi:inst\|q\[0\] 2 REG LC_X34_Y2_N5 1 " "Info: 2: + IC(5.084 ns) + CELL(0.590 ns) = 7.149 ns; Loc. = LC_X34_Y2_N5; Fanout = 1; REG Node = 'sopi:inst\|q\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "5.674 ns" { data_in[0] sopi:inst|q[0] } "NODE_NAME" } "" } } { "sopi.vhd" "" { Text "C:/altera/quartus51/my project/pro3/sopi.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.065 ns ( 28.89 % ) " "Info: Total cell delay = 2.065 ns ( 28.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.084 ns ( 71.11 % ) " "Info: Total interconnect delay = 5.084 ns ( 71.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "7.149 ns" { data_in[0] sopi:inst|q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.149 ns" { data_in[0] data_in[0]~out0 sopi:inst|q[0] } { 0.000ns 0.000ns 5.084ns } { 0.000ns 1.475ns 0.590ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.959 ns + " "Info: + Micro setup delay of destination is 0.959 ns" {  } { { "sopi.vhd" "" { Text "C:/altera/quartus51/my project/pro3/sopi.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "load destination 2.882 ns - Shortest register " "Info: - Shortest clock path from clock \"load\" to destination register is 2.882 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns load 1 CLK PIN_29 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 9; CLK Node = 'load'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "" { load } "NODE_NAME" } "" } } { "pro5.bdf" "" { Schematic "C:/altera/quartus51/my project/pro3/pro5.bdf" { { 288 48 216 304 "load" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.299 ns) + CELL(0.114 ns) 2.882 ns sopi:inst\|q\[0\] 2 REG LC_X34_Y2_N5 1 " "Info: 2: + IC(1.299 ns) + CELL(0.114 ns) = 2.882 ns; Loc. = LC_X34_Y2_N5; Fanout = 1; REG Node = 'sopi:inst\|q\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "1.413 ns" { load sopi:inst|q[0] } "NODE_NAME" } "" } } { "sopi.vhd" "" { Text "C:/altera/quartus51/my project/pro3/sopi.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.583 ns ( 54.93 % ) " "Info: Total cell delay = 1.583 ns ( 54.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.299 ns ( 45.07 % ) " "Info: Total interconnect delay = 1.299 ns ( 45.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "2.882 ns" { load sopi:inst|q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.882 ns" { load load~out0 sopi:inst|q[0] } { 0.000ns 0.000ns 1.299ns } { 0.000ns 1.469ns 0.114ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "7.149 ns" { data_in[0] sopi:inst|q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.149 ns" { data_in[0] data_in[0]~out0 sopi:inst|q[0] } { 0.000ns 0.000ns 5.084ns } { 0.000ns 1.475ns 0.590ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "2.882 ns" { load sopi:inst|q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.882 ns" { load load~out0 sopi:inst|q[0] } { 0.000ns 0.000ns 1.299ns } { 0.000ns 1.469ns 0.114ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk d_out\[6\] sipo:inst1\|q\[6\] 11.750 ns register " "Info: tco from clock \"clk\" to destination pin \"d_out\[6\]\" through register \"sipo:inst1\|q\[6\]\" is 11.750 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.814 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.814 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_122 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_122; Fanout = 16; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "" { clk } "NODE_NAME" } "" } } { "pro5.bdf" "" { Schematic "C:/altera/quartus51/my project/pro3/pro5.bdf" { { 184 48 216 200 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.634 ns) + CELL(0.711 ns) 7.814 ns sipo:inst1\|q\[6\] 2 REG LC_X34_Y20_N7 2 " "Info: 2: + IC(5.634 ns) + CELL(0.711 ns) = 7.814 ns; Loc. = LC_X34_Y20_N7; Fanout = 2; REG Node = 'sipo:inst1\|q\[6\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "6.345 ns" { clk sipo:inst1|q[6] } "NODE_NAME" } "" } } { "sipo.vhd" "" { Text "C:/altera/quartus51/my project/pro3/sipo.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 27.90 % ) " "Info: Total cell delay = 2.180 ns ( 27.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.634 ns ( 72.10 % ) " "Info: Total interconnect delay = 5.634 ns ( 72.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "7.814 ns" { clk sipo:inst1|q[6] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.814 ns" { clk clk~out0 sipo:inst1|q[6] } { 0.000ns 0.000ns 5.634ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "sipo.vhd" "" { Text "C:/altera/quartus51/my project/pro3/sipo.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.712 ns + Longest register pin " "Info: + Longest register to pin delay is 3.712 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sipo:inst1\|q\[6\] 1 REG LC_X34_Y20_N7 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y20_N7; Fanout = 2; REG Node = 'sipo:inst1\|q\[6\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "" { sipo:inst1|q[6] } "NODE_NAME" } "" } } { "sipo.vhd" "" { Text "C:/altera/quartus51/my project/pro3/sipo.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.588 ns) + CELL(2.124 ns) 3.712 ns d_out\[6\] 2 PIN PIN_176 0 " "Info: 2: + IC(1.588 ns) + CELL(2.124 ns) = 3.712 ns; Loc. = PIN_176; Fanout = 0; PIN Node = 'd_out\[6\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "3.712 ns" { sipo:inst1|q[6] d_out[6] } "NODE_NAME" } "" } } { "pro5.bdf" "" { Schematic "C:/altera/quartus51/my project/pro3/pro5.bdf" { { 96 496 672 112 "d_out\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 57.22 % ) " "Info: Total cell delay = 2.124 ns ( 57.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.588 ns ( 42.78 % ) " "Info: Total interconnect delay = 1.588 ns ( 42.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "3.712 ns" { sipo:inst1|q[6] d_out[6] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.712 ns" { sipo:inst1|q[6] d_out[6] } { 0.000ns 1.588ns } { 0.000ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "7.814 ns" { clk sipo:inst1|q[6] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.814 ns" { clk clk~out0 sipo:inst1|q[6] } { 0.000ns 0.000ns 5.634ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "C:/altera/quartus51/my project/pro3/db/pro3.quartus_db" { Floorplan "C:/altera/quartus51/my project/pro3/" "" "3.712 ns" { sipo:inst1|q[6] d_out[6] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.712 ns" { sipo:inst1|q[6] d_out[6] } { 0.000ns 1.588ns } { 0.000ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}