pro3.map.rpt

VHDL语言编写的 SPI总线控制器。。

+----------------------------------+-----------------+------------------------------------+----------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 17    ;
;     -- Combinational with no register       ; 1     ;
;     -- Register only                        ; 16    ;
;     -- Combinational with a register        ; 0     ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 0     ;
;     -- 3 input functions                    ; 1     ;
;     -- 2 input functions                    ; 0     ;
;     -- 1 input functions                    ; 0     ;
;     -- 0 input functions                    ; 0     ;
;         -- Combinational cells for routing  ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 17    ;
;     -- arithmetic mode                      ; 0     ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 8     ;
;                                             ;       ;
; Total registers                             ; 16    ;
; I/O pins                                    ; 21    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 16    ;
; Total fan-out                               ; 60    ;
; Average fan-out                             ; 1.58  ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                    ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |pro5                      ; 17 (0)      ; 16           ; 0           ; 21   ; 0            ; 1 (0)        ; 16 (0)            ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |pro5               ;
;    |sipo:inst1|            ; 8 (8)       ; 8            ; 0           ; 0    ; 0            ; 0 (0)        ; 8 (8)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |pro5|sipo:inst1    ;
;    |sopi:inst|             ; 9 (9)       ; 8            ; 0           ; 0    ; 0            ; 1 (1)        ; 8 (8)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |pro5|sopi:inst     ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------+
; User-Specified and Inferred Latches               ;
+-----------------------------------------------+---+
; Latch Name                                    ;   ;
+-----------------------------------------------+---+
; sopi:inst|q[0]                                ;   ;
; Number of user-specified and inferred latches ; 1 ;
+-----------------------------------------------+---+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 16    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 1     ;
; Number of registers using Asynchronous Load  ; 7     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/altera/quartus51/my project/pro3/pro3.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Mon Jul 31 23:24:37 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off pro3 -c pro3
Warning: Can't analyze file -- file C:/altera/quartus51/my project/pro3/Vhdl1.vhd is missing
Warning: Can't analyze file -- file C:/altera/quartus51/my project/pro3/Vhdl2.vhd is missing
Warning: Can't analyze file -- file C:/altera/quartus51/my project/pro3/pro3.vhd is missing
Info: Found 2 design units, including 1 entities, in source file sipo.vhd
    Info: Found design unit 1: sipo-a
    Info: Found entity 1: sipo
Info: Found 2 design units, including 1 entities, in source file sopi.vhd
    Info: Found design unit 1: sopi-a
    Info: Found entity 1: sopi
Warning: Can't analyze file -- file C:/altera/quartus51/my project/pro3/pro3.gdf is missing
Info: Found 1 design units, including 1 entities, in source file pro3.bdf
    Info: Found entity 1: pro3
Info: Found 1 design units, including 1 entities, in source file pro4.bdf
    Info: Found entity 1: pro4
Info: Found 1 design units, including 1 entities, in source file pro5.bdf
    Info: Found entity 1: pro5
Info: Found 1 design units, including 1 entities, in source file pro6.bdf
    Info: Found entity 1: pro6
Info: Elaborating entity "pro5" for the top level hierarchy
Info: Elaborating entity "sopi" for hierarchy "sopi:inst"
Warning (10492): VHDL Process Statement warning at sopi.vhd(16): signal "data_in" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10631): VHDL Process Statement warning at sopi.vhd(13): signal or variable "q" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "q" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Elaborating entity "sipo" for hierarchy "sipo:inst1"
Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN
    Warning: Converting TRI node "inst7" that feeds logic to a wire
Info: Implemented 38 device resources after synthesis - the final resource count might be different
    Info: Implemented 12 input pins
    Info: Implemented 9 output pins
    Info: Implemented 17 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings
    Info: Processing ended: Mon Jul 31 23:24:40 2006
    Info: Elapsed time: 00:00:03