counterhle.vhd

来自「an implementation of fft 1024 with cos a」· VHDL 代码 · 共 40 行

--Counter with resetn and load enable 
--When load enable is high, it counts. 
--When load enable is low, it stops counting. 
--When a reset is triggered, it resets to zero.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity counterhle is 
  generic (  width: integer :=3); 
  port (   clock : in std_logic; 
   resetn : in std_logic; 
   load_enable : in std_logic; 
   countout : out std_logic_vector(width-1 downto 0); 
   hle : out std_logic 
     ); 
end counterhle; 
 
architecture behavior of counterhle is 
signal count : std_logic_vector(width-1 downto 0); 
signal hold_load_enable : std_logic; 
 begin
process(clock) 
begin 
 if (resetn='0')then 
     count <= (others => '0'); 
     hold_load_enable <='0'; 
elsif (clock'event and clock='1') then   
if (load_enable = '1' or hold_load_enable='1') then       
count <= unsigned(count) + '1';            
   else  
count <= (others =>'0');     
   end if; 
   if (unsigned(count)+'1')=0 then 
   hold_load_enable <= load_enable;         
   end if; 
  end if;
end process; 
countout <= count; 
hle <=hold_load_enable; 
end;