mux2_mmw.vhd

来自「an implementation of fft 1024 with cos a」· VHDL 代码 · 共 33 行

--Special 2 to 1 mux (mismatched width) 
--7/17/02 
--First input is data_width bits --
--bits --Second input is data_width+1 
-- inputores highest bit of second--Ign
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;


ENTITY mux2_mmw IS 
 GENERIC( data_width : integer := 35 
       );   
    PORT  (  s : in std_logic;    
            in0 : in std_logic_vector(data_width-1 downto 0);        
            in1: in std_logic_vector(data_width downto 0);        
            data: out  std_logic_vector(data_width-1 downto 0)       
    );     
END mux2_mmw ; 
 
-- hds interface_end 
ARCHITECTURE behavior OF mux2_mmw IS 
BEGIN 
process(in0,in1,s) 
begin
if s='0' then   
data<=in0;    
 else 
   data<=in1(data_width-1 downto 0); 
 end if; 
end process; 
END behavior;