fft_core.vhd

an implementation of fft 1024 with cos and sin generated by matlab.

-- N point FFT 
-- Uses R2^2SDF algorithm 
-- 
-- Generics used: 
-- N - number of points taken - powers of 2 onging from 8 to nly, ra 1024 points. 
 -- input_width of  - bit width the input vector 
 --twiddle width - width of the twiddle factors stored in the ROM  
 -- add_g - Adder growth - Adders grow 0 or 1 bits each time they are used 
--         Exculdes adders in the complex multiplier (that is handled by mult_g) 
 -- mult_g - multiplier growth - 0 to twiddle_width+1 - Growth during the complex 
--    multiplier stages 
 --
 -- Width of output vector is as follows (num_stages=log2(N): 
--    N      width 
 --   8,16    input_width + (num_stages * add_g) + mult_g
--   32,64   input_width + (num_dd_g) + 2*mult_g stages * a
 -- 128,256    input_width + (num_stages * add_g) + 3*mult_g
  -- 512,1024   input_width + (num_stages* add_g) + 4*mult_g

 -- Due to the way this system was made parameterizable, there are many signals 
 -- that will remain unconnected.  This is normal. 
 --
-- Default generics are for a simple 64 point FFT 
LIBRARY ieee; 
USE ieee.std_logic_1164.ALL; 
USE ieee.std_logic_arith.ALL; 
use work.fft_pkg.all; 
entity fft_core is 
generic (  input_width : integer :=12;   
twiddle_width : integer :=10;         
    N : integer :=64; 
    add_g : integer:=1;   --Either 0 or 1 only.         
    mult_g : integer :=9  --Can be any number from  0 to twiddle_width+1 
   ); 
  port (  clock : in std_logic; 
          resetn : in std_logic; 
          load_enable : in std_logic; 
          xin_r : in std_logic_vector(input_width-1 downto 0);        
          xin_i : in std_logic_vector(input_width-1 downto 0);
          Xout_r : out std_logic_vector (input_width+((log2(N)- 1)/2)*mult_g+log2(N)*add_g-1 downto 0);
      Xout_i : out std_logic_vector (input_width+((log2(N)-1)/2)*mult_g+log2(N)*add_g-1 downto 0)); 
end fft_core; 
 
architecture structure of fft_core is 
--Signal declarations 
constant num_stages: integer :=log2(N); 
 signal control: std_logic_vector(num_stages-1 downto 0);
type stage_array is array (1 to num_stages-1) of std_logic_vector(input_width+(num_stages*add_g)+(((num_stages-
1)/2)*mult_g)-1 downto 0); 
 signal stoscon_r: stage_array;
 signal stoscon_i: stage_array; 
  type rom_array is array (1 to (num_stages-1)/2) of std_logic_vector(twiddle_width-1 downto 0);
signal rtoscon_r: rom_array; 
signal rtoscon_i: rom_array; 
--component declarations 
component counterhle 
  generic (width : integer); 
  port (   clock : in std_logic; 
      resetn : in std_logic; 
       load_enable : in std_logic;
      countout :out std_logic_vector(width-1 downto 0)); 
end component; 
 
component rom1 
   generic (data_width :integer; address_width : integer); 
   port   (address    : IN     std_logic_vector (address_width-1 DOWNTO 0); 
           datar     : OUT    std_logic_vector (data_width-1 DOWNTO 0); 
           datai     : OUT    std_logic_vector (data_width-1 DOWNTO 0));      
end component; 
 
component rom2 
   generic (data_width : integer; address_width : integer);
   port  (address    : IN     std_logic_vector (address_width-1 DOWNTO 0);
          datar     : OUT std_logic_vector (data_width-1 DOWNTO 0); 
          datai     : OUT    std_logic_vector (data_width-1 DOWNTO 0)     
      ); 
end component; 
 
component rom3 
  generic (data_width : integer; address_width : integer); 
   port  (address    : IN     std_logic_vector (address_width-1 DOWNTO 0);
    datar     : OUT    std_logic_vector (data_width-1 DOWNTO 0);      
  
  datai     : OUT    std_logic_vector (data_width-1 DOWNTO 0) 
);      
end component; 

component rom4 
  generic (data_width : integer; address_width : integer); 
  port  (address    : IN     std_logic_vector (address_width-1 DOWNTO 0); 
           datar     : OUT    std_logic_vector (data_width-1 DOWNTO 0); 
           datai     : OUT    std_logic_vector (data_width-1 DOWNTO 0)     
   ); 
end component; 
 
component stage_I 
 generic  (data_width : INTEGER; add_g : INTEGER; shift_stages : INTEGER);
 port  (prvs_r :in std_logic_vector(data_width-1-add_g downto 0); 
prvs_i :in std_logic_vector(data_width-1-add_g downto 0); 
 s :in std_logic; clock : in std_logic;  resetn :in std_logic;

tonext_r :out std_logic_vector(data_width-1 downto 0); 
   tonext_i :out std_logic_vector(data_width-1 downto 0)); 
end component; 
 
component stage_II 
generic  (data_width : INTEGER; add_g : INTEGER; mult_g :INTEGER; twiddle_width : INTEGER; shift_stages : INTEGER);       
   port  (prvs_r :in std_logic_vector(data_width-1-add_g downto 0);
       prvs_i :in std_logic_vector(data_width-1-add_g downto 0);
        t: in std_logic; s :in std_logic; clock : in std_logic;
 
   resetn : in std_logic; 
    fromrom_r :in std_logic_vector(twiddle_width-1 downto 0);
   fromrom_i :in std_logic_vector(twiddle_width-1 downto 0); 
      tonext_r :out std_logic_vector(data_width+mult_g-1 downto 0);     
     tonext_i :out std_logic_vector(data_width+mult_g-1 downto 0)); 
end component;
 
component stage_I_last 
   generic  (data_width : INTEGER; add_g : INTEGER); 
    port    (prvs_r :in std_logic_vector(data_width-1-add_g downto 0); 
             prvs_i :in std_logic_vector(data_width-1-add_g downto 0); 
             s :in std_logic; clock : in std_logic; resetn : in std_logic;
             tonext_r :out std_logic_vector(data_width-1 downto 0);    
             tonext_i :out std_logic_vector(data_width-1 downto 0)); 
end component;   
component stage_II_last 
   generic  (data_width :INTEGER; add_g : INTEGER); 
   port  (prvs_r :in std_logic_vector(data_width-1-add_g downto 0);
    prvs_i :in std_logic_vector(data_width-1-add_g downto 0); 
    clock : in std_logic;     t :in std_logic; s :in std_logic;
    resetn :in std_logic; 
    tonext_r :out std_logic_vector(data_width-1 downto 0);    
    tonext_i :out std_logic_vector(data_width-1 downto 0)); 
end component;   
 
begin 
  controller : component counterhle
       generic map (width=>num_stages)  
       port map (  clock=>clock,resetn=>resetn,load_enable=>load_enable, countout=>control); 
		 
stages : for i in 1 to num_stages generate 
--  constant parity : integer :=i rem 2; 
--  constant shift_stages : integer := 2**(num_stages - i); 
 --  constant rom_loc : integer :=i/2;
--  constant data_width : integer :=input_width + (i*add_g) + (((i-1)/2)*mult_g); 
 --  constant s: integer :=(num_stages-i);
 --  constant t: integer :=(num_stages-i+1);
     initial_stage: if i=1 generate  
     initial_stage_I :  component stage_I
     generic map (data_width=>input_width + (i*add_g)+(((i-1)/2)*mult_g),add_g=>add_g, shift_stages=>2**(num_stages - i)) 
     port map (   
     prvs_r=>xin_r,prvs_i=>xin_i,s=>control((num_stages-i)),clock=>clock,resetn=>resetn, 
     tonext_r=>stoscon_r(i)(input_width + (i*add_g) + (((i-1)/2)*mult_g)-1 downto 0),
     tonext_i=>stoscon_i(i)(input_width + (i*add_g) + (((i-1)/2)*mult_g)-1 downto 0));
     end generate initial_stage; 
   
 even_stages: if ((i rem 2)=0) and (i/=num_stages) generate  
    inner_stage_II : component stage_II 
      generic map (data_width=>input_width + (i*add_g) +(((i-1)/2)*mult_g),
		             add_g=>add_g,
						 mult_g=>mult_g,
						 twiddle_width=>twiddle_width,          
                   shift_stages=>2**(num_stages - i))
      port map (  prvs_r=>stoscon_r(i-1)(input_width + 
 (i*add_g) + (((i-1)/2)*mult_g)-1-add_g downto 0),
  prvs_i=>stoscon_i(i-1)(input_width             
+ (i*add_g) + (((i-1)/2)*mult_g)-1-add_g downto 0), 
            t=>control((num_stages- i+1)),s=>control((num_stages-i)),clock=>clock,resetn=>resetn, 
        
 fromrom_r=>rtoscon_r(i/2),fromrom_i=>rtoscon_i(i/2), 
tonext_r=>stoscon_r(i)(input_width            
 + (i*add_g) + (((i-1)/2)*mult_g)+mult_g-1 downto 0),
  tonext_i=>stoscon_i(i)(input_width         
 +(i*add_g) + (((i-1)/2)*mult_g)+mult_g-1 downto 0)); 
            
    first_rom: if (i/2)=1 generate 
    rom_1 : component rom1      
    generic map (data_width=>twiddle_width, 
address_width=>(num_stages-i+1)+1) 
        port map (  address=>control((num_stages-i+1)downto 0),--+1
           
 datar=>rtoscon_r(i/2),datai=>rtoscon_i(i/2)); 
     end generate first_rom;
   
  second_rom: if (i/2)=2 generate  
rom_2 : component rom2      
generic map (data_width=>twiddle_width,        
 address_width=>(num_stages-i+1)+1)
port map (  address=>control((num_stages-i+1)downto 0),
      
 datar=>rtoscon_r(i/2),datai=>rtoscon_i(i/2)); 
  end generate second_rom; 
        
    third_rom: if (i/2)=3 generate 
      rom_3 : component rom3 
     generic map (data_width=>twiddle_width,
                  address_width=>(num_stages-i+1)+1) 
        port map (  address=>control((num_stages-i+1)downto 0),
                    datar=>rtoscon_r(i/2),datai=>rtoscon_i(i/2)); 
          end generate third_rom;      
     
    fourth_rom: if (i/2)=4 generate 
rom_4 : component rom4      
      generic map (data_width=>twiddle_width,  
      address_width=>(num_stages-i+1)+1)
    port map (  address=>control((num_stages-i+1)downto 0), 

datar=>rtoscon_r(i/2),datai=>rtoscon_i(i/2)); 
end  generate fourth_rom; 
           
  end generate even_stages; 
   
odd_stages: if (((i rem 2)=1) and (i/=num_stages)) and (i/=1)generate  
inner_stage_I : component stage_I      
    generic map (data_width=>input_width + (i*add_g) +  
(((i-1)/2)*mult_g),  
      add_g=>add_g, 
shift_stages=>2**(num_stages - i)) 
   port map (  prvs_r=>stoscon_r(i-1)(input_width + 
 (i*add_g) + (((i-1)/2)*mult_g)-1-add_g downto 0),
             prvs_i=>stoscon_i(i-1)(input_width
 + (i*add_g) + (((i-1)/2)*mult_g)-1-add_g downto 0), 
 s=>control((num_stages-i)),clock=>clock,resetn=>resetn,
 tonext_r=>stoscon_r(i)(input_width+(i*add_g) + (((i-1)/2)*mult_g)-1 downto 0), 
            tonext_i=>stoscon_i(i)(input_width+(i*add_g) + (((i-1)/2)*mult_g)-1 downto 0)); 
  end generate odd_stages; 
  
end_on_even: if (i=num_stages) and ((i rem 2)=0) generate   
    last_stage_II : component stage_II_last 
 generic map (data_width=>input_width + (i*add_g) +(((i-1)/2)*mult_g), add_g=>add_g) 
 port map ( prvs_r=>stoscon_r(i-1)(input_width +(i*add_g) + (((i-1)/2)*mult_g)-1-add_g downto 0), 
            prvs_i=>stoscon_i(i-1)(input_width + (i*add_g) + (((i-1)/2)*mult_g)-1-add_g downto 0), 
            t=>control((num_stages-i+1)), s=>control((num_stages-i)),clock=>clock,resetn=>resetn, 
            tonext_r=>Xout_r,
				tonext_i=>Xout_i);
  end generate end_on_even; 
   
  end_on_odd: if (i=num_stages) and ((i rem 2)=1) generate 
     last_stage_I : component stage_I_last
generic map (data_width=>input_width +(i*add_g) +       
(((i-1)/2)*mult_g), add_g=>add_g) 
    port map (  prvs_r=>stoscon_r(i-1)(input_width +
(i*add_g) + (((i-1)/2)*mult_g)-1-add_g downto 0), 
            prvs_i=>stoscon_i(i-1)(input_width 
+ (i*add_g) + (((i-1)/2)*mult_g)-1-add_g downto 0), 
            s=>control((num_stages-i)),clock=>clock,resetn=>resetn, 
             tonext_r=>Xout_r,
				 tonext_i=>Xout_i);
                      
        
  end generate end_on_odd; 
   
end generate stages; 
end;