stage_i_ last.vhd

an implementation of fft 1024 with cos and sin generated by matlab.

 -- Comp onent for Stages using BF2I (if BF2I is the last stage) 
--Input is a standard logic vector of data_width-add_g 
--data_width - width of the internal busses 
-- 1, if 0 then  - if 1, data_width grows by--add_g - Add growth variable
--0 
--Only 1 shift stage----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;


---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
--
----Component for Stages using BF2II (last stage only) 
--lier after it -When BF2II is th  multip-     e last butterfly, there is no
---add_g d logic vector of data_width--Input is a standar
--of the internal busses th --data_width - wid
--_ - Ad--add g  d growth variable - if 1, data_width grows by 1, if 0 then 
--0 
 
library IEEE; 
use IEEE.std_logic_1164.all; 
use ieee.std_logic_arith.all; 

entity stage_I_last is
 generic  (  data_width : INTEGER :=13;
             add_g : INTEGER := 1);  
 port  (  prvs_r :in std_logic_vector(data_width-1-add_g downto 0);
          prvs_i :in std_logic_vector(data_width-1-add_g downto 0); 
          s :in std_logic; 
          clock : in std_logic;
          resetn : in std_logic; 
          tonext_r :out std_logic_vector(data_width-1 downto 0);    
          tonext_i :out std_logic_vector(data_width-1 downto 0)   
            ); 
 end stage_I_last;
 
architecture structure of stage_I_last is 
 signal toreg_r : std_logic_vector(data_width-1 downto 0);
 signal toreg_i : std_logic_vector(data_width-1 downto 0);
 signal fromreg_r :std_logic_vector(data_width-1 downto 0); 
 signal fromreg_i :std_logic_vector(data_width-1 downto 0);
 
component shiftreg1 
   generic (data_width : integer);
   port (clock : IN std_logic; 
         read_data  : OUT    std_logic_vector (data_width-1 DOWNTO 0); 
         write_data : IN     std_logic_vector (data_width-1 DOWNTO 0); 
         resetn     : IN     std_logic 
         ); 
end component; 
 
component BF2I 
   generic (data_width : INTEGER;
            add_g: INTEGER);  
   port    (fromreg_r :in std_logic_vector(data_width-1 downto 0); 
            fromreg_i :in std_logic_vector(data_width-1 downto 0); 
            prvs_r :in std_logic_vector(data_width-add_g-1 downto 0);
            prvs_i :in std_logic_vector(data_width-add_g-1 downto 0);
            s : in std_logic;
            toreg_r :out std_logic_vector(data_width-1 downto 0);
   
            toreg_i :out std_logic_vector(data_width-1 downto 0);     
            tonext_r :out std_logic_vector(data_width-1 downto 0);  
             tonext_i :out std_logic_vector(data_width-1 downto 0)); 
end component; 
 
begin 
regr : shiftreg1 
    generic map (data_width=>data_width)
    port map (clock=>clock, read_data=>fromreg_r, 
            write_data=>toreg_r, resetn=>resetn);
regi : shiftreg1 
    generic map (data_width=>data_width) 
    port map (clock=>clock, read_data=>fromreg_i, 
     write_data=>toreg_i, resetn=>resetn);
btrfly : BF2I 
    generic map (data_width=>data_width, add_g=>add_g)  
    port map (  fromreg_r=>fromreg_r, fromreg_i=>fromreg_i, 
	 prvs_r=>prvs_r, 
	 prvs_i=>prvs_i, 
    s=>s,      
    toreg_r=>toreg_r, toreg_i=>toreg_i, 
    tonext_r=>tonext_r, tonext_i=>tonext_i); 
end;