fft.vhd

an implementation of fft 1024 with cos and sin generated by matlab.

LIBRARY ieee; 
USE ieee.std_logic_1164.ALL; 
USE ieee.std_logic_arith.ALL; 
use work.fft_pkg.all; 
 
entity fft is 
   generic (  N : integer :=1024;--number of samples
             Serial_in : integer :=1; --1/0 serial/parallel    in 
             Serial_out: integer :=1; --1/0 serial/parallel   out 
             Output_order_in_natural: integer :=0; --1/0    output in natural/bit rev. order 
             m : integer :=12; --bit width of input        
             add_g : integer :=1; --Growth during adders, 1 or 0 
             mult_g : integer :=4; --growth during multipliers, up to twiddle_width+1  
             twiddle_width : integer :=10   );         
port (  --parameter-dependent ports  
        xrsi : in std_logic_vector(m-1 downto 0) :=(others=>'0'); 
        xisi : in std_logic_vector(m-1 downto 0) :=(others=>'0'); 
        xrpi : in ioarray(0 to N-1) :=(others =>(m-1 downto 0=>'0'));      
        xipi : in ioarray(0 to N-1) :=(others =>(m-1 downto 0=>'0')); 
		  
        Xrso : out std_logic_vector(m+((log2(N)-1)/2)*mult_g+log2(N)*add_g-1 downto 0); 
        Xiso : out std_logic_vector(m+((log2(N)-1)/2)*mult_g+log2(N)*add_g-1 downto 0);
        Xrpo : out ioarray(0 to N-1) :=(others =>(m+((log2(N)-1)/2)*mult_g+log2(N)*add_g-1 downto 0 =>'0')); 
        Xipo : out ioarray(0 to N-1) :=(others=>(m+((log2(N)-1)/2)*mult_g+log2(N)*add_g-1 downto 0 =>'0'));
--required ports      
        clk : in std_logic;
        load_enable :in std_logic;
        resetn : in std_logic ); 
end fft; 
architecture structure of fft is 
constant num_stages : integer :=log2(N); 
 constant w : integer := m+((num_stages-1)/2)*mult_g+num_stages*add_g;
 signal incore_r : std_logic_vector(m-1 downto 0);
 signal incore_i : std_logic_vector(m-1 downto 0);
 signal  outcore_r : std_logic_vector(w-1 downto 0);
 signal outcore_i : std_logic_vector(w-1 downto 0);
component fft_core 
  generic (input_width: integer; 
   twiddle_width: integer; 
   N : integer; 
   add_g : integer; 
   mult_g : integer); 
  port (  clock : in std_logic; 
   resetn : in std_logic; 
   load_enable : in std_logic;    
xin_r : in std_logic_vector(input_width-1 downto 0);        
       xin_i : in std_logic_vector(input_width-1 downto 0);
      Xout_r :out std_logic_vector (input_width+((log2(N)-1)/2)*mult_g+log2(N)*add_g-1 downto 0);
    Xout_i : out std_logic_vector (input_width+((log2(N)-1)/2)*mult_g+log2(N)*add_g-1 downto 0)
);      
end component; 
 
component s2pconv 
  generic (width: integer; 
   N: integer; 
   Output_order_in_natural: integer
      ); 
   port (  clock : in std_logic;
       load_enable :in std_logic; 
       resetn : in std_logic;      
       pdata_r : out ioarray(0 to N-1);  
       pdata_i : out ioarray(0 to N-1);      
       Xout_r : in std_logic_vector (width-1 downto 0);       
       Xout_i : in std_logic_vector (width-1 downto 0)
   ); 
end component; 
component p2sconv 
  generic (input_width : integer; N : integer); 
   port ( clock : in std_logic; 
   load_enable : in std_logic; 
   resetn : in std_logic; 
        pdata_r :in ioarray(0 to N-1);
        pdata_i : in ioarray(0 to N-1);
       xin_r : out std_logic_vector (input_width-1 downto 0); 
       xin_i : out std_logic_vector(input_width-1 downto 0) 
   ); 
end component; 
 
begin 
 
fft_main: fft_core 
  generic map (input_width=>m, twiddle_width=>twiddle_width, N=>N,  
add_g=>add_g,mult_g=>mult_g)
   port map (  clock=>clk, resetn=>resetn, load_enable=>load_enable,
  xin_r=>incore_r, xin_i=>incore_i,     
    Xout_r=>outcore_r, Xout_i=>outcore_i 
	 ); 
 
 s_in : if Serial_in=1 generate
 incore_r<=xrsi; 
  incore_i<=xisi; 
 end generate;
 
--p_in : if Serial_in=0 generate 
 -- input_conv : p2sconv 
--    generic map (input_width=>m, N=>N) 
--    port map (  clock=>clk, load_enable=>load_enable, 
--resetn=>resetn, 
--      pdata_r=>xrpi, 
--      pdata_i=>xipi, 
-- - -     xin_r=>incore_r, xin_i=>incore_i);
--end  generate ;   
 
s_out : if Serial_out=1 generate 
 Xrso<=outcore_r; 
 Xiso<=outcore_i; 
end generate; 
 
--p_out : if Serial_out=0 generate 
--  output_conv : s2pconv 
--   generic map (width=>w, N=>N, 
--Output_order_in_natural=>Output_order_in_natural) 
--    port map (  clock=>clk, load_enable=>load_enable, 
--se , resetn=>re tn
--      pdata_r=>xrpo, 
--      pdata_i=>xipo, 
--tcore_i); --      Xout_r=>outcore_r, Xout_i=>ou
--end generate; 
 
end;