comp_mult.vhd

an implementation of fft 1024 with cos and sin generated by matlab.

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:12:54 11/03/2008 
-- Design Name: 
-- Module Name:    comp_mult - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;


---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity comp_mult is 
 
generic (   inst_width1 : INTEGER := 14; 
      inst_width2 : INTEGER := 14   
        ); 
 
port  ( Re1  : in std_logic_vector(inst_width1-1 downto 0); 
        Im1  : in std_logic_vector(inst_width1-1 downto 0);  
        Re2  : in std_logic_vector(inst_width2-1 downto 0);  
        Im2  : in std_logic_vector(inst_width2-1 downto 0); 
        Re   : out std_logic_vector(inst_width1 + inst_width2 downto 0);          

        Im: out std_logic_vector(inst_width1 + inst_width2 downto 0)             
 );
 end comp_mult; 
 
 architecture behavior of  comp_mult is
--multiplier outputs 
signal product1 :std_logic_vector(inst_width1+inst_width2-1 downto 0);--re1*re2 
signal product2 :std_logic_vector(inst_width1+inst_width2-1 downto 0);--m1*im2 -i
signal product3 :std_logic_vector(inst_width1+inst_width2-1 downto 0); 
signal product4 :std_logic_vector(inst_width1+inst_width2-1 downto 0); 
component adder 
 generic (inst_width:integer); 
        port ( 
        inst_A : in std_logic_vector(inst_width-1 downto 0);               
        inst_B : in std_logic_vector(inst_width-1 downto 0);               
        SUM : out std_logic_vector(inst_width downto 0)); 
 
end component; 
 
 
component subtract 
 generic (inst_width:integer); 
  port (       
inst_A : in std_logic_vector(inst_width-1 downto 0);              
inst_B : in std_logic_vector(inst_width-1 downto 0);              
DIFF : out std_logic_vector(inst_width downto 0)); 
end  component ; 
 
 
component multiplier  
 generic (inst_width1:integer; 
  inst_width2:integer 
  ); 
  port ( 
  inst_A : in std_logic_vector(inst_width1-1 downto 0); 
  inst_B : in std_logic_vector(inst_width2-1 downto 0);              
  PRODUCT_inst : out std_logic_vector(inst_width1+inst_width2-1 downto 0) 
              );
end component;
begin 
 
        U1 : multiplier 
generic map( inst_width1=>inst_width1,inst_width2=>inst_width2)
port map ( inst_A => Re1, inst_B => Re2, PRODUCT_inst =>product1 ); 
           
U2 : multiplier 
    generic map( inst_width1=>inst_width1, inst_width2=>inst_width2) 
     port map( inst_A => Im1, inst_B => Im2, PRODUCT_inst => product2 );            

 
        U3 : multiplier 
      generic map( inst_width1=>inst_width1, 
inst_width2=>inst_width2) 
         port   map( inst_A => Re1, inst_B => Im2, PRODUCT_inst =>product3 ); 
  
      U4 : multiplier   
generic map( inst_width1=>inst_width2,inst_width2=>inst_width1)       
      port map ( inst_A => Re2, inst_B => Im1, PRODUCT_inst =>product4); 
 
           U5 : subtract
generic map (inst_width=>inst_width1+inst_width2)         
port map(inst_A => product1, inst_B => product2, DIFF =>Re ); 
 
U6 : adder         
generic map ( inst_width=>inst_width1+inst_width2)         
port map ( inst_A => product3, inst_B => product4, SUM =>Im ); 
 
end;