fft_filed_tb.vhd

an implementation of fft 1024 with cos and sin generated by matlab.

--File I/O version of the test bench 
--reads in a file called testvec, outputs to a file called data.out. 
--Only handles serial input/output. 
--Only needs a clock input, outputs the fft output in bit reversed order. 
 
LIBRARY ieee; 
USE ieee.std_logic_1164.ALL; 
USE ieee.std_logic_arith.ALL; 
USE std.textio.ALL; 
USE work.fft_pkg.all; 
 
 
entity fft_filed_tb is 
generic (  N : integer :=64; --number of points   
         m : integer :=12; --input width
         add_g : integer :=1; --adder growth
         mult_g : integer :=9; --Growth of the multipliers; 
         twiddle_width : integer :=10 --width of twiddle   roms factor
  );    
port (  clock : in std_logic;   
  Xout_r : out std_logic_vector (m+((log2(N)-1)/2)*mult_g+log2(N )* add_g-1 downto 0);
    Xout_i : out std_logic_vector (m+((log2(N)-1)/2)*mult_g+log2(N)*add_g-1 downto 0)
 );     
end fft_filed_tb; 

architecture stateflow of fft_filed_tb is 
 
 -- converts a character into a std_logic
 
  function char_to_stdl(c: character) return std_logic is
    variable sl: std_logic; 
  begin   
      case c is 
        when 'U' =>  
           sl := 'U';  
        when 'X' => 
           sl := 'X'; 
        when '0' =>  
           sl := '0'; 
        when '1' =>  
           sl := '1';            
        when 'Z' =>  
           sl := 'Z'; 

when 'W' =>  
           sl := 'W'; 
        when 'L' =>  
           sl := 'L'; 
        when 'H' =>  
           sl := 'H'; 
        when '-' =>  
           sl := '-'; 
        when others => 
           sl := 'X';  
    end case; 
   return sl; 
  end char_to_stdl; 
 
 
-- converts a string into std_logic_vector 
  function str_to_stdvec(s: string) return  std_logic_vector is
   variable slv: std_logic_vector(s'high-s'low downto 0);
  variable k: integer; 
begin 
   k := s'high-s'low; 
  for i in s'range loop 
     slv(k) := char_to_stdl(s(i)); 
     k      := k - 1; 
  end loop; 
  return slv; 
end str_to_stdvec;  
 
  --converts a std_logic_vector to a string           
 function stdvec_to_str(inp: std_logic_vector) return string is
 variable temp: string(inp'left+1 downto 1) := (others => 'X');
begin 
     for i in inp'reverse_range loop 
     if (inp(i) = '1') then      
          temp(i+1) := '1'; 
        elsif (inp(i) = '0') then 
            temp(i+1) := '0';  
        end if; 
  end loop; 
    return temp; 
end;-- function stdvec_to_str; 
--
--	constant clkprd : time:=400 ns;
--	signal 	clock : std_logic:='0';
--
signal resetn : std_logic; 
signal load_enable : std_logic; 
signal xrsi : std_logic_vector (m-1 downto 0); 
signal xisi : std_logic_vector (m-1 downto 0); 
signal outdata_r : std_logic_vector (m+((log2(N)-1)/2)*mult_g+log2(N)*add_g-1 downto 0);  
signal outdata_i : std_logic_vector (m+((log2(N)-1)/2)*mult_g+log2(N)*add_g-1 downto 0);  
 
component fft 
  generic (  N : integer; 
         m :integer; 
      add_g : integer;  

       mult_g : integer; 
         twiddle_width : integer);
  port (  clk : in std_logic; 
          resetn : in std_logic;      
          load_enable : in std_logic;      
          xrsi : in std_logic_vector(m-1 downto 0);
          xisi : in std_logic_vector(m-1 downto 0); 
          Xrso : out std_logic_vector (m+((log2(N)-1)/2)*mult_g+log2(N)*add_g-1 downto 0); 
          Xiso : out std_logic_vector (m+((log2(N)-1)/2)*mult_g+log2(N)*add_g-1 downto 0)
);      
end component; 
 
begin 
fft_core : fft 
   generic map (N=>N, m=>m, add_g=>add_g, mult_g=>mult_g,  
                twiddle_width=>twiddle_width)
   port map (   clk=>clock,resetn=>resetn,load_enable=>load_enable,
                xrsi=>xrsi, xisi=>xisi, 
                Xrso=>outdata_r, Xiso=>outdata_i);
process(outdata_r,outdata_i) 
begin
  Xout_r<= outdata_r;  
 Xout_i<=outdata_i; 
end process; 
--

--clockgen: process
--begin
--        clock <= '0';
--        wait for clkprd/2;
--        clock <= '1';
--        wait for clkprd/2;
--end process;
--

--process 
--variable i: integer:=1;
--begin
--     resetn<='1';
--     load_enable<='0';
--     wait until clock'EVENT and clock='1';
-- 	  while i <= 64 loop
--     resetn<='0';
--     load_enable<='1';
--     xrsi<="001010000000";
--     xisi<="101010101010";
--     i:=i+1;
--	  end loop;
--end process;
--


process(clock)
  file my_output : TEXT open WRITE_MODE is "data.out"; 
  file my_input : TEXT open READ_MODE is "testvec"; 
  variable my_data, file_line :LINE; 
  variable stimulus_in : STRING (m*2+2 downto 1); 
  variable data_out :string ((m+((log2(N)-1)/2)*mult_g+log2(N)*add_g)*2 downto 1); 
  variable stim_stdl : std_logic_vector(m*2+1 downto 0);  
begin 
if ((clock'event and clock='0') and not endfile(my_input)) then  
     data_out:=stdvec_to_str(outdata_r) &
     stdvec_to_str(outdata_i);
     write(my_data,data_out); 
     writeline(my_output,my_data);
     readline(my_input,file_line);   
     read(file_line,stimulus_in);
     stim_stdl:=str_to_stdvec(stimulus_in);
      elsif ((clock'event and clock='1') and not endfile(my_input))
then 
     resetn<=stim_stdl(m*2+1);
     load_enable<=stim_stdl(m*2);
     xrsi<=stim_stdl(m*2-1 downto m);
     xisi<=stim_stdl(m-1 downto 0);
 end if;   
end process; 
end stateflow;