shiftregn.vhd

an implementation of fft 1024 with cos and sin generated by matlab.

-- hds header_start 
--r, data_width bits wide. -n st- age shift registe
 
liBRARy ieee;
USE ieee.std_logic_1164.ALL; 
USE ieee.std_logic_arith.ALL;
 
 
ENTITY shiftregN IS 
   GENERIC(  
      data_width : integer := 25; 
      n   : integer := 4 
   ); 
   PORT(  
      clock      : IN     std_logic; 
      read_data  : OUT    std_logic_vector (data_width-1 DOWNTO 0); 
      write_data : IN           std_logic_vector (data_width-1 DOWNTO 0); 
      resetn     : IN     std_logic       
   ); 
 
-- Declarations 
 
END shiftregN ; 
 
-- hds interface_end 
 ARCHITECTURE behavior OF shiftregN IS
subtype reg is std_logic_vector(data_width-1 downto 0); 
  type regArray is array (integer range <>) of reg;
 
   signal registerFile : regArray(1 to n-1); 
 BEGIN
process(Clock, resetn) 
 variable i: integer;
begin 
if (resetn='0') then   
for i in 1 to  (n-1) loop    
      registerFile(i) <= (others => '0');
      read_data <= (others => '0');    
   
  end loop;  
  elsif (Clock'event and Clock='1') then 
    registerFile(1) <= write_data;    
    for i in 2 to n-1 loop  
 registerFile(i) <= registerFile(i-1);      
   end loop; 
    read_data <= registerFile(n-1);      
       
end if;  
end process; 
END behavior;