rom4.vhd

an implementation of fft 1024 with cos and sin generated by matlab.

-- Rom file for twiddle factors 
-- rom4.vhd contains16 points of 10 width 
-- for a64 point fft.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;


ENTITY rom4 IS
GENERIC(
        data_width : integer :=10;
        address_width : integer :=4
    );
    PORT(
        address :in std_logic_vector (3  downto 0);
        datar : OUT std_logic_vector (data_width-1 DOWNTO 0);
        datai : OUT std_logic_vector (data_width-1 DOWNTO 0)
    );
end rom4;
ARCHITECTURE behavior OF rom4 IS

 BEGIN

process(address)
begin
    case address is
   when "0000" => datar <= "0111111111";datai <= "0000000000"; --0
   when "0001" => datar <= "0101101001";datai <= "1010010111"; --8
   when "0010" => datar <= "0000000000";datai <= "1000000001"; --16
   when "0011" => datar <= "1010010111";datai <= "1010010111"; --24
   when "0100" => datar <= "0111111111";datai <= "0000000000"; --0
   when "0101" => datar <= "0111011000";datai <= "1100111100"; --4
   when "0110" => datar <= "0101101001";datai <= "1010010111"; --8
   when "0111" => datar <= "0011000100";datai <= "1000101000"; --12
   when "1000" => datar <= "0111111111";datai <= "0000000000"; --0
   when "1001" => datar <= "0011000100";datai <= "1000101000"; --12
   when "1010" => datar <= "1010010111";datai <= "1010010111"; --24
   when "1011" => datar <= "1000101000";datai <= "0011000100"; --36
        when "1100" => datar <= "0111111111";datai <= "0000000000"; --0
        when "1101" => datar <= "0111111111";datai <= "0000000000"; --0
        when "1110" => datar <= "0111111111";datai <= "0000000000"; --0
        when "1111" => datar <= "0111111111";datai <= "0000000000"; --0
        when others => for i in data_width-1 downto 0 loop
            datar(i)<='0';datai(i)<='0';end loop;
    end case;

end process;
END behavior;