msm3000_registers.csv

This file defines all the register names and addresses.

VOC_DEC_VOX_THRESHOLD,0x3000470,W,0FFFFFFF
VOC_DEC_VOX_THRESHOLD,0x300046C,W,0FFFFFFF
VOC_DEC_BNG_FLOOR,0x3000480,W,0FFFFFFF
VOC_DEC_BNG_FLOOR,0x300047C,W,0FFFFFFF
DTMF_DURATION,0x3000488,W,0FFFFFFF
DTMF_DURATION,0x3000484,W,0FFFFFFF
DTMF_HIGH,0x3000490,W,0FFFFFFF
DTMF_HIGH,0x300048C,W,0FFFFFFF
DTMF_LOW,0x3000498,W,0FFFFFFF
DTMF_LOW,0x3000494,W,0FFFFFFF
DTMF_VOLUME,0x30004A0,W,0FFFFFFF
DTMF_VOLUME,0x300049C,W,0FFFFFFF
VOC_DEC_VOLUME,0x30004A8,W,0FFFFFFF
VOC_DEC_VOLUME,0x30004A4,W,0FFFFFFF
PCM_PAD_CTL,0x30004AC,W,0FFFFFFF
PCM_CTL_WORD_MSB,0x30004B0,W,0FFFFFFF
PCM_CTL_WORD_LSB,0x30004B4,W,0FFFFFFF
VOC_ENCDEC_IO_CTL,0x30004C0,W,0FFFFFFF
CLEAR_VOC_ENC_INT,0x30004C4,W,0FFFFFFF
CLEAR_VOC_DEC_INT,0x30004C8,W,0FFFFFFF
VOC_DEC_PACKET,0x30004CC,W,0FFFFFFF
VOC_FL_RAM_ADDR,0x30004E8,W,0FFFFFFF
VOC_FL_RAM_DATA,0x30004EC,W,0FFFFFFF
CDMA Vocoder Status and Read Registers,CDMA Vocoder Status and Read Registers,CDMA Vocoder Status and Read Registers,CDMA Vocoder Status and Read Registers
VOC_ENC_PCM_RD,0x3000404,R,0FFFFFFF
VOC_ENC_PCM_RD,0x3000400,R,0FFFFFFF
VOC_DEC_PCM_RD,0x300040C,R,0FFFFFFF
VOC_DEC_PCM_RD,0x3000408,R,0FFFFFFF
VOC_STATUS,0x3000410,R,0FFFFFFF
VOC_ENC_PACKET,0x3000440,R,0FFFFFFF
VOC_ENC_SAMP_CNT,0x3000444,R,0FFFFFFF
VOC_DEC_SAMP_CNT,0x3000448,R,0FFFFFFF
DTMF STATUS0,0x3000440,R,0FFFFFFF
DTMF STATUS1,0x3000444,R,0FFFFFFF
DTMF STATUS2,0x3000448,R,0FFFFFFF
DFM Vocoder Control and Write Registers,DFM Vocoder Control and Write Registers,DFM Vocoder Control and Write Registers,DFM Vocoder Control and Write Registers
VOC_RESET,0x3000400,W,0FFFFFFF
TX_PCM_CTL,0x3000418,W,0FFFFFFF
RX_PCM_CTL,0x300041C,W,0FFFFFFF
TEST_CTL_1,0x3000430,W,0FFFFFFF
MODE_CTL,0x300043C,W,0FFFFFFF
FM_AUDIO_CONFIG,0x300045C,W,0FFFFFFF
FM_TEST_CTL,0x3000460,W,0FFFFFFF
VOC_FM_CONFIG,0x3000464,W,0FFFFFFF
SAT_LEVEL,0x3000468,W,0FFFFFFF
SAT_THRESHOLD,0x300046C,W,0FFFFFFF
TX_DEVIATION_LIMIT,0x3000470,W,0FFFFFFF
FM_TX_GAIN,0x3000474,W,0FFFFFFF
FM_RX_GAIN,0x3000478,W,0FFFFFFF
DTMF_DURATION,0x3000488,W,0FFFFFFF
DTMF_DURATION,0x3000484,W,0FFFFFFF
DTMF_HIGH,0x3000490,W,0FFFFFFF
DTMF_HIGH,0x300048C,W,0FFFFFFF
DTMF_LOW,0x3000498,W,0FFFFFFF
DTMF_LOW,0x3000494,W,0FFFFFFF
DTMF_FM_RX_GAIN,0x300049C,W,0FFFFFFF
DTMF_FM_TX_GAIN,0x30004A0,W,0FFFFFFF
PCM_PAD_CTL,0x30004AC,W,0FFFFFFF
PCM_CTL_WORD_MSB,0x30004B0,W,0FFFFFFF
VOC_DEC_PACKET,0x30004CC,W,0FFFFFFF
DFM Vocoder Status and Read Registers,DFM Vocoder Status and Read Registers,DFM Vocoder Status and Read Registers,DFM Vocoder Status and Read Registers
VOC_STATUS,0x3000410,R,0FFFFFFF
FM_STATUS,0x3000438,R,0FFFFFFF
DFM Registers,DFM Registers,DFM Registers,DFM Registers
DFM_INITIAL,0x3000500,W,0FFFFFFF
DFM_DC_OFFSET_GAIN,0x3000504,W,0FFFFFFF
DFM_AGC_REF,0x3000508,W,0FFFFFFF
DFM_AGC_ACC_MIN,0x300050C,W,0FFFFFFF
DFM_RX_AGC_FILTER,0x300050C,R,0FFFFFFF
DFM_AGC_ACC_MAX,0x3000510,W,0FFFFFFF
DFM_RX_AGC_RSSI,0x3000510,R,0FFFFFFF
DFM_AGC_GAIN,0x3000514,W,0FFFFFFF
DFM_FREQ_LOOP_CONFIG,0x3000518,W,0FFFFFFF
DFM_PDM_CONFIG,0x300051C,W,0FFFFFFF
DFM_DC_PDM_0,0x3000520,W,0FFFFFFF
DFM_DC_PDM_1,0x3000524,W,0FFFFFFF
DFM_DC_PDM_2,0x3000528,W,0FFFFFFF
DFM_RXAGC_PDM_0,0x300052C,W,0FFFFFFF
DFM_RXAGC_PDM_1,0x3000570,W,0FFFFFFF
DFM_FREQ_PDM_0,0x3000530,W,0FFFFFFF
DFM_FREQ_PDM_1,0x3000534,W,0FFFFFFF
DFM_VOC_INTF_CONFIG,0x3000538,W,0FFFFFFF
TXWBD_INTF_BUFFER_0,0x3000540,W,0FFFFFFF
TXWBD_INTF_BUFFER_1,0x3000544,W,0FFFFFFF
DFM_MAX_TX_PWR_0,0x3000548,W,0FFFFFFF
DFM_TXWBD_STATUS,0x3000548,R,0FFFFFFF
DFM_DC_PDM_3,0x300053C,W,0FFFFFFF
DFM_MAX_TX_PWR_1,0x300054C,W,0FFFFFFF
DFM_FREQ_SENS_GAIN,0x3000550,W,0FFFFFFF
DFM_TXFM_CONFIG,0x3000554,W,0FFFFFFF
MIN1,0x3000560,W,0FFFFFFF
MIN1,0x300055C,W,0FFFFFFF
MIN1,0x3000558,W,0FFFFFFF
RXWBD_UP_INTF_BUFFER,0x3000560,R,0FFFFFFF
RXWBD_UP_INTF_BUFFER,0x300055C,R,0FFFFFFF
RXWBD_UP_INTF_BUFFER,0x3000558,R,0FFFFFFF
DFM_RXWBD_BANDWIDTH,0x3000564,W,0FFFFFFF
RXWBD_UP_INTF_BUFFER_MSB,0x3000564,R,0FFFFFFF
DFM_RXWBD_CONFIG_0,0x3000568,W,0FFFFFFF
DFM_WORD_SYNC_COUNT,0x3000568,R,0FFFFFFF
DFM_RXWBD_RD,0x300056C,R,0FFFFFFF
DFM_RXWBD_CONFIG_1,0x3000574,W,0FFFFFFF
DFM_SLOT_PDM_CTL,0x300057C,W,0FFFFFFF
DFM_SLOT_CTL,0x3000580,W,0FFFFFFF
DFM_SLOT_STATUS,0x3000580,R,0FFFFFFF
DFM_DPLL_WU_TIMER,0x3000584,W,0FFFFFFF
DFM_SYNC_WU_TIMER,0x3000588,W,0FFFFFFF
DFM_DATA_WU_TIMER,0x300058C,W,0FFFFFFF
DFM_STREAM_SLOT_TIMER,0x3000590,W,0FFFFFFF
CDMA Sleep Control,CDMA Sleep Control,CDMA Sleep Control,CDMA Sleep Control
SLEEP_CTL,0x3000600,W,0FFFFFFF
SLEEP_STATUS,0x3000600,R,0FFFFFFF
POWER_DOWN_SLEEP_INTERVAL,0x3000610,W,0FFFFFFF
POWER_DOWN_SLEEP_INTERVAL,0x300060C,W,0FFFFFFF
POWER_DOWN_WU_TIME,0x3000618,W,0FFFFFFF
SLEEP_XTAL_FREQ_ERR,0x3000614,R,0FFFFFFF
POWER_DOWN_CHIPX8_SLEEP_TIME,0x300061C,W,0FFFFFFF
POWER_DOWN_CHIPX8_COUNT,0x300061C,R,0FFFFFFF
Interrupt Controller,Interrupt Controller,Interrupt Controller,Interrupt Controller
INT_CLEAR_0,0x3000620,W,0FFFFFFF
INT_CLEAR_1,0x3000624,W,0FFFFFFF
INT_STATUS_0,0x3000620,R,0FFFFFFF
INT_STATUS_1,0x3000624,R,0FFFFFFF
IRQ_MASK_0,0x3000628,W,0FFFFFFF
IRQ_MASK_1,0x300062C,W,0FFFFFFF
IRQ_MASK_RD_0,0x3000628,R,0FFFFFFF
IRQ_MASK_RD_1,0x300062C,R,0FFFFFFF
FIQ_MASK_0,0x3000638,W,0FFFFFFF
FIQ_MASK_1,0x300063C,W,0FFFFFFF
FIQ_RD_MASK_0,0x3000638,R,0FFFFFFF
FIQ_RD_MASK_1,0x300063C,R,0FFFFFFF
INT_POLARITY,0x3000648,W,0FFFFFFF
GPIO,GPIO,GPIO,GPIO
GPIO_IN_0,0x3000660,R,0FFFFFFF
GPIO_IN_1,0x3000664,R,0FFFFFFF
GPIO_IN_2,0x3000668,R,0FFFFFFF
GPIO_IN_3,0x300066C,R,0FFFFFFF
GPIO_IN_4,0x3000670,R,0FFFFFFF
GPIO_OUT_0,0x3000660,W,0FFFFFFF
GPIO_OUT_1,0x3000664,W,0FFFFFFF
GPIO_OUT_2,0x3000668,W,0FFFFFFF
GPIO_OUT_3,0x300066C,W,0FFFFFFF
GPIO_OUT_4,0x3000670,W,0FFFFFFF
GPIO_TSEN_0,0x3000674,W,0FFFFFFF
GPIO_TSEN_1,0x3000678,W,0FFFFFFF
GPIO_TSEN_2,0x300067C,W,0FFFFFFF
GPIO_TSEN_3,0x3000680,W,0FFFFFFF
GPIO_TSEN_4,0x3000684,W,0FFFFFFF
GPIO_INT_IN,0x3000688,R,0FFFFFFF
GPIO_INT_OUT,0x3000688,W,0FFFFFFF
GPIO_INT_TSEN,0x300068C,W,0FFFFFFF
GPIO_FUNCTION_SEL,0x3000690,W,0FFFFFFF
KEYSENSE_RD,0x3000694,R,0FFFFFFF
PA_ON_CTL,0x3000698,W,0FFFFFFF
PA_ON_STATUS,0x3000698,R,0FFFFFFF
YAMN1 and RINGER M/N Counter,YAMN1 and RINGER M/N Counter,YAMN1 and RINGER M/N Counter,YAMN1 and RINGER M/N Counter
YAMN1_CLK_MDIV,0x30006A4,W,0FFFFFFF
YAMN1_CLK_MDIV,0x30006A0,W,0FFFFFFF
YAMN1_CLK_NDIV,0x30006AC,W,0FFFFFFF
YAMN1_CLK_NDIV,0x30006AB,W,0FFFFFFF
YAMN1_CLK_DUTY,0x30006B4,W,0FFFFFFF
YAMN1_CLK_DUTY,0x30006B0,W,0FFFFFFF
RINGER_MN_A_DUTY,0x30006BC,W,0FFFFFFF
RINGER_MN_A_DUTY,0x30006B8,W,0FFFFFFF
RINGER_MN_A_NDIV,0x30006C4,W,0FFFFFFF
RINGER_MN_A_NDIV,0x30006C0,W,0FFFFFFF
RINGER_MN_A_MDIV,0x30006C8,W,0FFFFFFF
RINGER_MN_B_DUTY,0x30006D0,W,0FFFFFFF
RINGER_MN_B_DUTY,0x30006CC,W,0FFFFFFF
RINGER_MN_B_NDIV,0x30006D8,W,0FFFFFFF
RINGER_MN_B_NDIV,0x30006D4,W,0FFFFFFF
RINGER_MN_B_MDIV,0x30006DC,W,0FFFFFFF
Time Tick Interrupt and General Purpose Timer,Time Tick Interrupt and General Purpose Timer,Time Tick Interrupt and General Purpose Timer,Time Tick Interrupt and General Purpose Timer
TIME_TICK_CTL,0x30006E0,W,0FFFFFFF
TIME_TICK_INT_MSB,0x30006E0,R,0FFFFFFF
GPTIMER_COUNT,0x30006E4,R/W,0FFFFFFF
GPTIMER_CTL,0x30006E8,W,0FFFFFFF
PDM1and PDM2,PDM1and PDM2,PDM1and PDM2,PDM1and PDM2
TCXO_PDM_CTL,0x30006EC,W,0FFFFFFF
PDM2_CTL,0x30006F0,W,0FFFFFFF
PDM1_CTL,0x30006F4,W,0FFFFFFF
ADC Interface,ADC Interface,ADC Interface,ADC Interface
ADC_RESET,0x3000700,W,0FFFFFFF
ADC_STAT,0x3000700,R,0FFFFFFF
ADC_DATA_WR,0x3000704,W,0FFFFFFF
ADC_DATA_RD,0x3000704,R,0FFFFFFF
Auxiliary Codec Control,Auxiliary Codec Control,Auxiliary Codec Control,Auxiliary Codec Control
CODEC_CTL1,0x3000720,W,0FFFFFFF
CODEC_CTL2,0x3000724,W,0FFFFFFF
MSM Clocks Control,MSM Clocks Control,MSM Clocks Control,MSM Clocks Control
MSM_CLK_CTL1,0x3000740,W,0FFFFFFF
MSM_CLK_CTL2,0x3000744,W,0FFFFFFF
MSM_CLK_CTL3,0x3000748,W,0FFFFFFF
MSM_CLK_CTL4,0x300074C,W,0FFFFFFF
MSM_CLK_CTL5,0x3000754,W,0FFFFFFF
Version Register,Version Register,Version Register,Version Register
HARDWARE_REVISION_NUMBER,0x300075C,R,0FFFFFFF
SBI Controller,SBI Controller,SBI Controller,SBI Controller
SBI_CLK_CTL,0x3000780,W,0FFFFFFF
SBI_STATUS,0x3000780,R,0FFFFFFF
SBI_CTL,0x3000784,W,0FFFFFFF
SBI_BYPASS,0x3000788,W,0FFFFFFF
SBI_BYPASS_RD,0x3000788,R,0FFFFFFF
SBI_WR,0x300078C,W,0FFFFFFF
SBI_RD,0x300078C,R,0FFFFFFF
SBI_START_CTL,0x3000790,W,0FFFFFFF
UART Registers,UART Registers,UART Registers,UART Registers
UART_MR1,0x30007AC,R/W,0FFFFFFF
UART_MR2,0x30007B0,R/W,0FFFFFFF
UART_CSR,0x30007B4,W,0FFFFFFF
UART_SR,0x30007B4,R,0FFFFFFF
UART_TF,0x30007B8,W,0FFFFFFF
UART_RF,0x30007B8,R,0FFFFFFF
UART_CR,0x30007BC,W,0FFFFFFF
UART_MISR,0x30007BC,R,0FFFFFFF
UART_IMR,0x30007C0,W,0FFFFFFF
UART_ISR,0x30007C0,R,0FFFFFFF
UART_IPR,0x30007C4,R/W,0FFFFFFF
UART_TFWR,0x30007C8,R/W,0FFFFFFF
UART_RFWR,0x30007CC,R/W,0FFFFFFF
UART_HCR,0x30007D0,R/W,0FFFFFFF
UART_MREG_MSB,0x30007D4,R/W,0FFFFFFF
UART_NREG_MSB,0x30007D8,R/W+C407,0FFFFFFF
UART_DREG_MSB,0x30007DC,R/W,0FFFFFFF
UART_MND_LSB,0x30007E0,R/W,0FFFFFFF
ARM Clock/Power Control Registers,ARM Clock/Power Control Registers,ARM Clock/Power Control Registers,ARM Clock/Power Control Registers
UP_CLK_CTL1,0x4800000,W,0FFFFFFF
UP_CLK_CTL2,0x4800004,W,0FFFFFFF
Reset and Pause Registers,Reset and Pause Registers,Reset and Pause Registers,Reset and Pause Registers
PAUSE_TIMER,0x4800020,W,0FFFFFFF
RESET_STATUS,0x4800020,R,0FFFFFFF
ASB Decoder Register,ASB Decoder Register,ASB Decoder Register,ASB Decoder Register
ASB_DECODE_CTL,0x4800070,W,0FFFFFFF
Memory Map and Bus Sizer Registers,Memory Map and Bus Sizer Registers,Memory Map and Bus Sizer Registers,Memory Map and Bus Sizer Registers
MEMORY_WAIT1,0x4800080,W,0FFFFFFF
MEMORY_WAIT2,0x4800084,W,0FFFFFFF
GP_CS_N_WAIT,0x4800088,W,0FFFFFFF
MSM_WAIT,0x480008C,W,0FFFFFFF
CS_CTL,0x4800090,W/R,0FFFFFFF
BSIZER_CTL1,0x4800094,W,0FFFFFFF
BSIZER_CTL2,0x4800098,W,0FFFFFFF
LCD_CTL,0x480009C,W,0FFFFFFF
GPIO_INT_ADDR_SEL,0x48000A0,W,0FFFFFFF