fft_test.tcl

这里边有EDA设计常用模块的源代码

# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.

# Quartus II: Generate Tcl File for Project
# File: fft_test.tcl
# Generated on: Tue Oct 10 19:22:59 2006

# Load Quartus II Tcl Project package
package require ::quartus::project

set need_to_close_project 0
set make_assignments 1

# Check that the right project is open
if {[is_project_open]} {
	if {[string compare $quartus(project) "fft_test"]} {
		puts "Project fft_test is not open"
		set make_assignments 0
	}
} else {
	# Only open if not already open
	if {[project_exists fft_test]} {
		project_open -revision fft_test fft_test
	} else {
		project_new -revision fft_test fft_test
	}
	set need_to_close_project 1
}

# Make assignments
if {$make_assignments} {
	set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.0
	set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:19:27  OCTOBER 09, 2006"
	set_global_assignment -name LAST_QUARTUS_VERSION 5.0
	set_global_assignment -name SOURCE_FILE fft.cmp
	set_global_assignment -name VERILOG_FILE fft_test.v
	set_global_assignment -name VERILOG_FILE dds.v
	set_global_assignment -name VERILOG_FILE disp_controller.v
	set_global_assignment -name VERILOG_FILE display_load_data.v
	set_global_assignment -name VERILOG_FILE div_freq.v
	set_global_assignment -name VERILOG_FILE fft.v
	set_global_assignment -name VERILOG_FILE fft_data_switch.v
	set_global_assignment -name VERILOG_FILE fft_load_data.v
	set_global_assignment -name VERILOG_FILE key_board.v
	set_global_assignment -name VERILOG_FILE sample.v
	set_global_assignment -name VERILOG_FILE vga.v
	set_global_assignment -name VHDL_FILE "D:/MegaCore/fft-v2.1.3/lib/fft_pack.vhd"
	set_global_assignment -name VERILOG_FILE "E:/EDA/fft_test/fft.v"
	set_global_assignment -name DUTY_CYCLE 50 -section_id CLKDRUSER
	set_global_assignment -name FMAX_REQUIREMENT "105.0 MHz" -section_id CLKDRUSER
	set_global_assignment -name DUTY_CYCLE 50 -section_id TCKUTAP
	set_global_assignment -name FMAX_REQUIREMENT "105.0 MHz" -section_id TCKUTAP
	set_global_assignment -name DUTY_CYCLE 50 -section_id UPDATEUSER
	set_global_assignment -name FMAX_REQUIREMENT "105.0 MHz" -section_id UPDATEUSER
	set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
	set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
	set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
	set_global_assignment -name FAMILY Cyclone
	set_global_assignment -name USER_LIBRARIES "D:/MegaCore/fft-v2.1.3/lib;"
	set_global_assignment -name DEVICE EP1C12Q240C8
	set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
	set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS OUTPUT DRIVING AN UNSPECIFIED SIGNAL"
	set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
	set_global_assignment -name ENABLE_CLOCK_LATENCY ON
	set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE EPCS4
	set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
	set_location_assignment PIN_28 -to clock
	set_location_assignment PIN_121 -to key[0]
	set_location_assignment PIN_122 -to key[1]
	set_location_assignment PIN_123 -to key[2]
	set_location_assignment PIN_124 -to key[3]
	set_location_assignment PIN_143 -to key[4]
	set_location_assignment PIN_141 -to key[5]
	set_location_assignment PIN_158 -to key[6]
	set_location_assignment PIN_156 -to key[7]
	set_location_assignment PIN_136 -to dig[7]
	set_location_assignment PIN_137 -to dig[6]
	set_location_assignment PIN_138 -to dig[5]
	set_location_assignment PIN_139 -to dig[4]
	set_location_assignment PIN_161 -to dig[3]
	set_location_assignment PIN_162 -to dig[2]
	set_location_assignment PIN_159 -to dig[1]
	set_location_assignment PIN_160 -to dig[0]
	set_location_assignment PIN_164 -to seg[7]
	set_location_assignment PIN_163 -to seg[6]
	set_location_assignment PIN_166 -to seg[5]
	set_location_assignment PIN_165 -to seg[4]
	set_location_assignment PIN_168 -to seg[3]
	set_location_assignment PIN_167 -to seg[2]
	set_location_assignment PIN_170 -to seg[1]
	set_location_assignment PIN_169 -to seg[0]
	set_location_assignment PIN_38 -to da_clk
	set_location_assignment PIN_8 -to da_mode
	set_location_assignment PIN_46 -to da_data[9]
	set_location_assignment PIN_13 -to da_data[8]
	set_location_assignment PIN_14 -to da_data[7]
	set_location_assignment PIN_16 -to da_data[6]
	set_location_assignment PIN_18 -to da_data[5]
	set_location_assignment PIN_20 -to da_data[4]
	set_location_assignment PIN_23 -to da_data[3]
	set_location_assignment PIN_41 -to da_data[2]
	set_location_assignment PIN_43 -to da_data[1]
	set_location_assignment PIN_45 -to da_data[0]
	set_location_assignment PIN_11 -to ad_noe
	set_location_assignment PIN_236 -to ad_datin[7]
	set_location_assignment PIN_238 -to ad_datin[6]
	set_location_assignment PIN_240 -to ad_datin[5]
	set_location_assignment PIN_2 -to ad_datin[4]
	set_location_assignment PIN_4 -to ad_datin[3]
	set_location_assignment PIN_5 -to ad_datin[2]
	set_location_assignment PIN_7 -to ad_datin[1]
	set_location_assignment PIN_12 -to ad_datin[0]
	set_location_assignment PIN_62 -to disp_dato[0]
	set_location_assignment PIN_65 -to disp_dato[1]
	set_location_assignment PIN_67 -to disp_dato[2]
	set_location_assignment PIN_73 -to disp_dato[3]
	set_location_assignment PIN_104 -to disp_dato[4]
	set_location_assignment PIN_100 -to disp_dato[5]
	set_location_assignment PIN_98 -to disp_dato[6]
	set_location_assignment PIN_94 -to disp_dato[7]
	set_location_assignment PIN_113 -to hsync
	set_location_assignment PIN_108 -to vsync
	set_location_assignment PIN_152 -to reset_n
	set_instance_assignment -name CLOCK_SETTINGS TCKUTAP -to altera_internal_jtag~TCKUTAP
	set_instance_assignment -name CLOCK_SETTINGS CLKDRUSER -to altera_internal_jtag~CLKDRUSER
	set_instance_assignment -name CLOCK_SETTINGS UPDATEUSER -to altera_internal_jtag~UPDATEUSER

	# Commit assignments
	export_assignments

	# Close project
	if {$need_to_close_project} {
		project_close
	}
}