uart.tb

使用vhdl语言在用fpga实现vart。

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;

ENTITY TestBench IS
END TestBench;

ARCHITECTURE HTWTestBench OF TestBench IS

COMPONENT uart
    PORT (mclkx16, read, write, reset : IN std_logic;
	   data : INOUT std_logic_vector(7 downto 0);
		-- receiver input signal, error, and status flags
		rx : IN std_logic;
		rxrdy : OUT std_logic;
	   parityerr : OUT std_logic;
		framingerr : OUT std_logic;
		overrun : OUT std_logic;
		
		-- transmitter output signal and status flag
		tx : OUT std_logic;
		txrdy : OUT std_logic);
END COMPONENT;

      SIGNAL mclkx16Signal : std_logic := '1';   -- initialized to 1
      SIGNAL readSignal : std_logic := '1';  -- de-assert read initially
      SIGNAL writeSignal : std_logic := '1'; -- de-assert write initially
      SIGNAL resetSignal :  std_logic := '1';   -- initialized to 1
	   SIGNAL dataSignal :  std_logic_vector(7 downto 0);
		-- receiver input signal, error, and status flags
		SIGNAL rxSignal :  std_logic;
		SIGNAL rxrdySignal :  std_logic ;   
	   SIGNAL parityerrSignal :  std_logic;
		SIGNAL framingerrSignal :  std_logic;
		SIGNAL overrunSignal :  std_logic;
		
		-- transmitter output signal and status flag
		SIGNAL txSignal :  std_logic;
		SIGNAL txrdySignal :  std_logic;

      -- storage of dataSignal
      SIGNAL data_written : std_logic_vector(7 downto 0); 
      SIGNAL data_received : std_logic_vector(7 downto 0);

		CONSTANT baudrate : time := 500 ns;  -- specify the baudrate for the simulation
	  
BEGIN

-- instantiate UART top level entity into test bench
    U1 : uart
		PORT MAP (mclkx16 => mclkx16Signal,
		          read => readSignal,
		          write => writeSignal,
		          reset => resetSignal,
		          data => dataSignal,
		          rx => rxSignal,
		          rxrdy => rxrdySignal,
		          parityerr => parityerrSignal,
		          framingerr => framingerrSignal,
		          overrun => overrunSignal,
		          tx => txSignal,
		          txrdy => txrdySignal);

-- *********begin test bench**********

-- generate 16 times baudrate clock frequency
-- (mclkx16Signal = baudrate/16)
-- baudrate/(16*2) used to generate half clock cycle;
	mclkx16Signal <= (Not mclkx16Signal) after (baudrate/(16*2)); 

-- Reset Uart  
	resetSignal <= '0' after 2000 ns;

-- feeding back output from transmitter to the input of receiver
	rxSignal <= txSignal after 1 ns;


--core test program
	self_check : PROCESS
	   -- procedure declaration
		-- declared in process due to assignment to writeSignal.
		-- this procedure writes data to the transmitter
		-- timing can be modified to model any CPU write cycle
	   PROCEDURE write_to_transmitter (data : IN integer) IS
        VARIABLE din : std_logic_vector(7 downto 0);
      BEGIN
         din :=conv_std_logic_vector(data,8);
         writeSignal <= '0';
         WAIT FOR 100 ns;
         dataSignal <= din;
         WAIT FOR 50 ns;
         writeSignal <= '1';
         data_written <= din;
         WAIT FOR 20 ns;
      END PROCEDURE;

		-- procedure declaration
		-- declared in process due to assignment to readSignal
		-- this procedure reads out data from the receiver
		-- timing can be modified to model any CPU read cycle
		PROCEDURE read_out_receiver (data_in : IN std_logic_vector(7 downto 0)) IS
      BEGIN
         readSignal <= '0';
         WAIT FOR 25 ns;
         data_received <= data_in;
         WAIT FOR 75 ns;
         readSignal <= '1';
      END PROCEDURE;

		-- this procedure compares the data sent and received,
		-- and flags for any error it encounters.
		-- Comparison is done just prior to next data transmission,
		-- and after previous received data has been read out.
      PROCEDURE compare_data (dataw, datar : IN std_logic_vector(7 downto 0)) IS
      VARIABLE data_wr, data_rv : integer range 0 to 255;
      BEGIN
        data_wr := conv_integer(dataw);
		  data_rv := conv_integer(datar);
        ASSERT (data_wr = data_rv) 
            REPORT "Simulation FAILED!!  data_written = "&integer'image(data_wr)&
                   "  ===>  data_received = "&integer'image(data_rv)  SEVERITY FAILURE;
	   END PROCEDURE;
	BEGIN
	   WAIT UNTIL mclkx16Signal'EVENT and mclkx16Signal='1';
      IF resetSignal = '0' THEN

		FOR i IN 0 TO 255 LOOP   -- start test loop;
		   write_to_transmitter(i);      -- write_to_transmitter procedure call;
	      WAIT UNTIL (rxrdySignal = '1');  -- wait for rxrdy
		   read_out_receiver(dataSignal);            -- read_out_receiver procedure call;
		   compare_data(data_written, data_received);                 -- compare_data procedure call;
		   
		END LOOP;
      
      REPORT "Simulation OK! Passed all possible combinations successfully!" SEVERITY NOTE;
     END IF;
   END PROCESS;


END HTWTestBench;